https://dwarffortresswiki.org/api.php?action=feedcontributions&feedformat=atom&user=Green+SpriteDwarf Fortress Wiki - User contributions [en]2026-05-08T21:08:32ZUser contributionsMediaWiki 1.35.11https://dwarffortresswiki.org/index.php?title=Mist&diff=258143Mist2021-06-14T01:54:41Z<p>Green Sprite: Changed old diagram to new ones (<diagram>). Now all diagram use the same format and it looks better</p>
<hr />
<div>{{Quality|Exceptional|12:00, 5 September 2019 (UTC)}}<br />
{{av}}<br />
[[File:mist_example.jpg|thumb|170px|right|Feels good on the skin, maybe.]]<br />
'''Mist''' is created by [[water]] [[Waterfall|falling]] from one [[Z-level]] to another, from [[DF2014:Ocean#Ocean_waves|ocean waves]], items or creatures skipping across water or just standard splashing. The mist is generated on levels below the top level (from which the water drops), but spreads out similarly to [[miasma]] and, therefore, can appear even on the top level, and lingers and spreads for a short time after any water stops falling. Walking through mist generates a happy [[thought]] for a dwarf, and can act to [[Cleaning|clean]] various contaminants off of dwarves. <br />
<br />
Mist is separate from [[magma mist]] and [[steam]].<br />
<br />
[[File:mist_preview.png|thumb|120px|right|Rampant [[screw pump]]s are a great mist source.]]<br />
<br />
==Generating Mist==<br />
=== Constructed waterfall ===<br />
The easiest method is simply to use a constant source of water ([[Screw pump|pumped]] or [[channel]]ed) and let it fall more than 1 z-level next to a path that dwarves use regularly. The actual tile (you only need one) that the water drops should not be part of the path, as dwarves will believe they are in 7/7 water and cancel jobs - a statue on that tile will prevent this nicely, or place the fall itself to the side of the path and make that a [[Traffic#Setting Traffic Areas|restricted traffic]] tile. <br />
<br />
[[Floor grate]]s or [[bars]] on every* tile adjacent to the water flow should be used as part of the drainage system (which should be larger than the intake system, just to be safe!), and to avoid [[mud]] on adjacent tiles. Use a door, hatch, floodgate or bridge linked to a [[lever]] to turn off the flow if/when desired.<br />
<br />
: (* when designing this, remember that grates/bars [[Cave-in|do not support]] floor tiles!)<br />
<br />
The problem with this setup is that this amount of constantly falling/flowing water can have a negative impact on your fps rate. Using a [[repeater]] to allow a non-constant flow, or linking the flow to a [[pressure plate]], where it will only fall when dwarves approach, will help this.<br />
<br />
=== Ring generator ===<br />
AncientEnemy [http://www.bay12forums.com/smf/index.php?topic=34407.0] devised a convenient way to generate mist. This method relies on the fact that [[screw pump|screw pumps]] pump [[water]] faster than water spreads out.[[Image:newmist.jpg|thumb|AncientEnemy's original simple mist generator.]]<br />
<br />
Simply put, screw pumps are daisy-chained (output to input) in a circle and then water is added to the system. Water is typically added by designating one of the inputs to the pump as a [[Pond]] and having dwarves fill it up. Once water is dropped from the floor above it is immediately sucked up by the next pump. Since there is falling water, mist is generated. Ahh, lovely waterfalls!<br />
<br />
Below is an example of a simple mist generator. The Z=0 level can be anything, a booze stockpile, [[barracks]] or even your [[Dwarven_atom_smasher|atom smasher]]. The z=-1 layer can also be identical to the z=0 level. Mist will also be generated there. Because the water never touches the floor there, you don't have to worry about muddy tiles.<br />
<diagram><br />
Pump Floor (z=1)<br />
▒▒▒▒▒▒<br />
▒.[#2:0]÷[#2:1]÷[#].▒<br />
▒[#2:1]÷ [#2:0]÷[#]▒ The water can go clockwise or counter clockwise.<br />
▒[#2:0]÷ [#2:1]÷[#]▒ Make sure your pumps are correctly aligned.<br />
▒.[#2:1]÷[#2:0]÷[#].▒<br />
▒▒▒▒▒▒<br />
</diagram><br />
A movie [http://mkv25.net/dfma/movie-1292-ubermistgenerator] best illustrates the operation. <br />
<br />
=== Stack generator ===<br />
<br />
A two-pump-stack can be used to lift a single tile of water and drop it back into the reservoir, generating mist (and [[Cleaning#Dwarven_Shower|cleaning dwarves]], if desired).<br />
<br />
<diagram><br />
<br />
sideview <br />
<br />
[#2:0]%%[#]_<br />
[#6:0]%%[#]_<br />
░░░░[#1:0]▄[#]░░░<br />
░░░░░░░░<br />
<br />
</diagram><br />
<br />
The lower (brown) pump (pumping right to left) raises the water from the reservoir on the right to floor level on the left, then the upper (green) pump (pumping left to right) raises that water to the air +2 z-levels above the reservoir. The water then falls through the floor grates ( _ ) into the reservoir, and the cycle can be repeated. Pump build order is important; build the green pump first, then the brown pump, to ensure the water is raised in a single tick. Since the water never sits at floor level, no containment walls are necessary (though mud will be created in the tile left of the brown pump). You can toggle power to the pumps as often as desired to provide happy thoughts without constant lag. If used for dwarf-cleaning, a water level of 2/7 or 3/7 will avoid job cancellations.<br />
<br />
=== Light aquifer ===<br />
If your embark location has a light aquifer, it is possible to build an unpowered mist generator-plus-bathing unit combination. You need two floors under the aquifer - lowest floor is for dwarves, second floor is for water to fall a z-level to create mist and to control the amount of water flow. It is also possible to dig out more of the aquifer to increase water flow if needed. You can use this water elsewhere or let it evaporate.{{Verify}}<br />
<br />
== General comments ==<br />
<!-- The extra spaces are for ease of editing only, and do not change the appearance of the page layout.--><br />
* Evaporation is nonexistent as long as the pumps are working and the water is moving, even above ground.{{Verify}}<br />
<br />
* Job cancellation spam is possible if the water is filled to 4/7 or greater and a dwarf walks where the water falls. Even then, this can be greatly reduced by setting them as [[traffic#Setting Traffic Areas|restricted traffic]] areas, or completely prevented by blocking access to these tiles without blocking the water, such as by placing a [[statue]] underneath.<br />
<br />
* Mud will form wherever the water falls. Subterranean [[tree]]s can sprout up and clog the system. Solutions to this problem include: [[statue]]s, [[road|paved roads]], constructed floors or [[fortification]]s, or to simply channel out the space once the mist generator is running.<br />
<br />
* These systems work best with a single tile of water (7/7, at most) due to the way water descends z-levels. Any additional water will overflow into nearby tiles.<br />
<br />
* Automated mist generators may significantly lower your [[Frames per second|FPS]], particularly if multiple generators are used.{{Verify}} This might be remedied by triggering via a [[repeater]] with a long delay or by one or more [[pressure plate]]s (perhaps set to activate by a passing dwarf).{{Verify}}<br />
<br />
{{Translation<br />
| dwarven = sôd<br />
| elvish = enure<br />
| goblin = guslo<br />
| human = sitsu<br />
}}<br />
<br />
{{Category|Thoughts}}<br />
{{Category|World}}<br />
{{Category|Physics}}<br />
[[Ru:Mist]]</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=DF2014_Talk:Scholar&diff=258116DF2014 Talk:Scholar2021-06-12T03:50:04Z<p>Green Sprite: </p>
<hr />
<div>Ok, copy pasting this here, until we can reword it into something readable:<br />
<br />
:Let's see, fort scholars... they do activity cycles, the length of which is 1-2 days (whether they are pondering or discussing etc.) Once they get through 50 cycles, it rolls 0-50 vs. the number of completed cycles minus 50 to see if they get "breakthrough credit." So at 51, they have a 2% chance, and at 100, they have a 100% chance. Then, it resets the cycle number to zero and gives them breakthrough credit, based on a skill roll plus 100 (for discuss, the other researchers contribute half of their summed skill rolls.) Based on the difficulty (1-4) of the topic, total lifetime breakthrough credit is then assigned a number of 50-sided dice. An easy topic is dice=credit/2500, then /5000, then /10000, then /20000 for level 4 topics. The number of dice cannot exceed 10. Then roll these dice -- if you get a 50 on any of them, discovery! This is a bit archaic, and I'm not suggesting it works particularly well. But that is how it works. Also: if they fail to get the breakthrough after the 50-sided rolls, they have a 2% chance of switching topics, or if their credit exceeds 100000, they always switch topics (though they keep the credit, so returning to the topic later gives them a decent chance at breakthrough.)<br />
<br />
from http://www.bay12forums.com/smf//index.php?topic=169696.msg8071983#msg8071983<br />
<br />
[[User:Therahedwig|Therahedwig]] ([[User talk:Therahedwig|talk]]) 17:39, 1 January 2020 (UTC)<br />
<br />
==Professions not working as stated==<br />
In the section called "Professions" it states a dwarf with high levels of critical thinking and a second skill are called sages. However, in one of my saves, a dwarf has the title of sage with only dabbling skill in critical thinking. The dwarf is a high master mathematician and accomplished logician.The information on what makes a dwarf a sage comes from http://www.bay12forums.com/smf/index.php?topic=154895.msg6711752#msg6711752 where Halnoth points it comes comes from their observation. I suspect a sage might be a dwarf that potentially belongs to more than one profession. For example, in my case the dwarf could be a mathematician or a philosopher, so the game assigns them the title of sage. [[User:Green Sprite|Green Sprite]] ([[User talk:Green Sprite|talk]]) 03:50, 12 June 2021 (UTC)</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258105User:Green Sprite2021-06-08T16:54:54Z<p>Green Sprite: </p>
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<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0].<br />
. Z=0<br />
.<br />
☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]] (pts converter).<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Adder==<br />
The adder used in the Dwarftel Core d1 is a kogge-stone adder, which is a type of carry-lookahead adder. It consists of 3 components chained in a certain way.<br />
<br />
Components:<br />
<diagram fg=7:0><br />
O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#] And gate<br />
[#7:1]╚╝[#]<br />
O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#] Xor gate<br />
[#7:1]╚╝[#]<br />
O══════════════════O<br />
OO[#]☼[#4:1]☼[#2:1]☼[#] (x and y) or z<br />
[#5:1]^[#0:0][@7:0]■[@#]☼[#1:1]☼☼<br />
[#7:1]╚╝<br />
</diagram><br />
In the and gate, power is fed to the rightmost gear assembly. Both gear assemblies are inverted. Each gear assembly is linked to one input, power goes into the pts converter only when both inputs are open.<br />
<br />
In the xor gate, power is fed to the gear assembly. The gear assembly is inverted and linked to both inputs. When either input, but not both, are open, power goes to the pts converter.<br />
<br />
In the last component, there are three non-commutative inputs. Power is fed to the green gear assembly {{Raw Tile|☼|#0F0}}. Input z is linked to the red gear assembly {{Raw Tile|☼|#F00}}. Inputs x and y are linked to either blue gear assembly {{Raw Tile|☼|#00F}}, creating an and gate. Both blue gears and the reg gear are inverted.<br />
<br />
The adder takes the following steps:<br />
# G0i = Ai and Bi. P0i = Ai xor Bi (both for 0 ≤ i < 8)<br />
# G1i = (P0i and G0(i-1)) or G0i. P1i = P0i and P0(i-1) (both for 1 ≤ i < 8)<br />
# G2i = (P1i and G1(i-2)) or G1i. P2i = P1i and P1(i-2) (both for 2 ≤ i < 8)<br />
# G3i = (P2i and G2(i-4)) or G2i. P3i = P2i and P2(i-4) (both for 4 ≤ i < 8)<br />
# Si = P(last)i xor G(last)(i-1)<br />
Where i is the bit index on the byte (0 being the least significant bit and 7 being the most significant bit). A and B are the registers used as inputs. P(last)i is the latest iteration of Pi. For example, P(last)1 is P1,1, since steps 3 and 4 don't apply to i=1. Similarly, G(last)i is the latest iteration of Gi.<br />
<br />
[[File:Kogge stone adder diagram.png|450px|The image shows how each step of the adder connects to the next step(s).]]<br />
<br />
The only delays are caused by pressure plates which turn off 99 ticks after a minecart stops pressing it. Just to be safe (and because minecarts might require some travel time) I will assume 103 ticks of delay per step. Since there's 5 steps in the process, there's a total of 515 ticks <br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a pts converter. The pts converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258104User:Green Sprite2021-06-08T05:15:27Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0].<br />
. Z=0<br />
.<br />
☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]] (pts converter).<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Adder==<br />
The adder used in the Dwarftel Core d1 is a kogge-stone adder, which is a type of carry-lookahead adder. It consists of 3 components chained in a certain way.<br />
<br />
Components:<br />
<diagram fg=7:0><br />
O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#] And gate<br />
[#7:1]╚╝[#]<br />
O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#] Xor gate<br />
[#7:1]╚╝[#]<br />
O══════════════════O<br />
OO[#]☼[#4:1]☼[#2:1]☼[#] (x and y) or z<br />
[#5:1]^[#0:0][@7:0]■[@#]☼[#1:1]☼☼<br />
[#7:1]╚╝<br />
</diagram><br />
In the and gate, power is fed to the rightmost gear assembly. Both gear assemblies are inverted. Each gear assembly is linked to one input, power goes into the pts converter only when both inputs are open.<br />
<br />
In the xor gate, power is fed to the gear assembly. The gear assembly is inverted and linked to both inputs. When either input, but not both, are open, power goes to the pts converter.<br />
<br />
In the last component, there are three non-commutative inputs. Power is fed to the green gear assembly {{Raw Tile|☼|#0F0}}. Input z is linked to the red gear assembly {{Raw Tile|☼|#F00}}. Inputs x and y are linked to either blue gear assembly {{Raw Tile|☼|#00F}}, creating an and gate. Both blue gears and the reg gear are inverted.<br />
<br />
The adder takes the following steps:<br />
# G0i = Ai and Bi. P0i = Ai xor Bi (both for 0 ≤ i < 8)<br />
# G1i = (P0i and G0(i-1)) or G0i. P1i = P0i and P0(i-1) (both for 1 ≤ i < 8)<br />
# G2i = (P1i and G1(i-2)) or G1i. P2i = P1i and P1(i-2) (both for 2 ≤ i < 8)<br />
# G3i = (P2i and G2(i-4)) or G2i. P3i = P2i and P2(i-4) (both for 4 ≤ i < 8)<br />
# Si = P(last)i xor G(last)(i-1)<br />
Where i is the bit index on the byte (0 being the least significant bit and 7 being the most significant bit). A and B are the registers used as inputs. P(last)i is the latest iteration of Pi. For example, P(last)1 is P1,1, since steps 3 and 4 don't apply to i=1. Similarly, G(last)i is the latest iteration of Gi.<br />
<br />
[[File:Kogge stone adder diagram.png|450px|The image shows how each step of the adder connects to the next step(s).]]<br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a pts converter. The pts converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=File:Kogge_stone_adder_diagram.png&diff=258103File:Kogge stone adder diagram.png2021-06-08T05:02:21Z<p>Green Sprite: </p>
<hr />
<div><br />
== Licensing ==<br />
{{PD-text}}</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258102User:Green Sprite2021-06-08T02:57:24Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0].<br />
. Z=0<br />
.<br />
☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]] (pts converter).<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Adder==<br />
The adder used in the Dwarftel Core d1 is a kogge-stone adder, which is a type of carry-lookahead adder. It consists of 3 components chained in a certain way.<br />
<br />
Components:<br />
<diagram fg=7:0><br />
O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#] And gate<br />
[#7:1]╚╝[#]<br />
O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#] Xor gate<br />
[#7:1]╚╝[#]<br />
O══════════════════O<br />
OO[#]☼[#4:1]☼[#2:1]☼[#] (x and y) or z<br />
[#5:1]^[#0:0][@7:0]■[@#]☼[#1:1]☼☼<br />
[#7:1]╚╝<br />
</diagram><br />
In the and gate, power is fed to the rightmost gear assembly. Both gear assemblies are inverted. Each gear assembly is linked to one input, power goes into the pts converter only when both inputs are open.<br />
<br />
In the xor gate, power is fed to the gear assembly. The gear assembly is inverted and linked to both inputs. When either input, but not both, are open, power goes to the pts converter.<br />
<br />
In the last component, there are three non-commutative inputs. Power is fed to the green gear assembly {{Raw Tile|☼|#0F0}}. Input z is linked to the red gear assembly {{Raw Tile|☼|#F00}}. Inputs x and y are linked to either blue gear assembly {{Raw Tile|☼|#00F}}, creating an and gate. Both blue gears and the reg gear are inverted.<br />
<br />
The adder takes the following steps:<br />
# G0i = Ai and Bi. P0i = Ai xor Bi (both for 0 ≤ i < 8)<br />
# G1i = (P0i and G0(i-1)) or G0i. P1i = P0i and P0(i-1) (both for 1 ≤ i < 8)<br />
# G2i = (P1i and G1(i-2)) or G1i. P2i = P1i and P1(i-2) (both for 2 ≤ i < 8)<br />
# G3i = (P2i and G2(i-4)) or G2i. P3i = P2i and P2(i-4) (both for 4 ≤ i < 8)<br />
# Si = P(last)i xor G(last)(i-1)<br />
Where i is the bit index on the byte (0 being the least significant bit and 7 being the most significant bit). A and B are the registers used as inputs. P(last)i is the latest iteration of Pi. For example, P(last)1 is P1,1, since steps 3 and 4 don't apply to i=1. Similarly, G(last)i is the latest iteration of Gi.<br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a pts converter. The pts converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258098User:Green Sprite2021-06-07T06:45:41Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0].<br />
. Z=0<br />
.<br />
☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]] (pts converter).<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Adder==<br />
The adder used in the Dwarftel Core d1 is a kogge-stone adder, which is a type of carry-lookahead adder. It consists of 3 components chained in a certain way.<br />
<br />
Components:<br />
<diagram fg=7:0><br />
O══════════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#] And gate |1|<br />
[#7:1]╚╝[#]<br />
O══════════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#] Xor gate |2|<br />
[#7:1]╚╝[#]<br />
O══════════════════════O<br />
OO[#]☼[#4:1]☼[#2:1]☼[#] (x and y) or z |3|<br />
[#5:1]^[#0:0][@7:0]■[@#]☼[#1:1]☼☼<br />
[#7:1]╚╝<br />
</diagram><br />
In the and gate, power is fed to the rightmost gear assembly. Both gear assemblies are inverted. Each gear assembly is linked to one input, power goes into the pts converter only when both inputs are open.<br />
<br />
In the xor gate, power is fed to the gear assembly. The gear assembly is inverted and linked to both inputs. When either input, but not both, are open, power goes to the pts converter.<br />
<br />
In the last component, there are three non-commutative inputs. Power is fed to the green gear assembly {{Raw Tile|☼|#0F0}}. Input z is linked to the red gear assembly {{Raw Tile|☼|#F00}}. Inputs x and y are linked to either blue gear assembly {{Raw Tile|☼|#00F}}, creating an and gate. Both blue gears and the reg gear are inverted.<br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a pts converter. The pts converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258097User:Green Sprite2021-06-07T06:23:40Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0].<br />
. Z=0<br />
.<br />
☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]].<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Adder==<br />
The adder used in the Dwarftel Core d1 is a kogge-stone adder, which is a type of carry-lookahead adder. It consists of 3 components chained in a certain way.<br />
<br />
Components:<br />
<diagram fg=5:0><br />
[#7:0]O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#7:0] Bitwise and<br />
[#7:1]╚╝[#7:0]<br />
O══════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#7:0] Bitwise xor<br />
[#7:1]╚╝[#7:0]<br />
O══════════════════O<br />
OO[#]☼☼[#7:0]☼ (x and y) or z<br />
[#5:1]^[#0:0][@7:0]■[@#]☼☼☼<br />
[#7:1]╚╝<br />
</diagram><br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a power to signal converter. The power to signal converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258096User:Green Sprite2021-06-07T05:42:20Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0].<br />
. Z=0<br />
.<br />
☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]].<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Adder==<br />
Components<br />
<diagram fg=5:0><br />
[#7:0]O══════════════════════════════════════O Operation:<br />
[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#7:0] Bitwise and<br />
[#7:1]╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝[#7:0]<br />
O══════════════════════════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#7:0] Bitwise xor<br />
[#7:1]╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝[#7:0]<br />
O══════════════════════════════════════O<br />
OO[#]☼☼[#7:0]☼OO[#]☼☼[#7:0]☼OO[#]☼☼[#7:0]☼OO[#]☼☼[#7:0]☼OO[#]☼☼[#7:0]☼OO[#]☼☼[#7:0]☼OO[#]☼☼[#7:0]☼OO[#]☼☼[#7:0]☼ (x and y) or z<br />
[#5:1]^[#0:0][@7:0]■[@#]☼☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼☼<br />
[#7:1]╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝<br />
</diagram><br />
Kogge-Stone Adder<br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a power to signal converter. The power to signal converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258094User:Green Sprite2021-06-07T00:23:02Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]<br />
║ ║ ║ ║ ║ ║ ║<br />
[#7:0].<br />
. Z=0<br />
.<br />
☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]].<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Adder==<br />
<diagram fg=7:0><br />
O══════════════════════════════O Operation: Output:<br />
[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@][#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼ Ai and Bi. G<br />
[#7:1]╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝<br />
O══════════════════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@#]☼[#5:1]^[#0:0][@7:0]■[@#]☼[#5:1]^[#0:0][@7:0]■[@#]☼[#5:1]^[#0:0][@7:0]■[@#]☼[#5:1]^[#0:0][@7:0]■[@#]☼[#5:1]^[#0:0][@7:0]■[@#]☼[#5:1]^[#0:0][@7:0]■[@#]☼[#5:1]^[#0:0][@7:0]■[@#]☼ Ai xor Bi. P0<br />
[#7:1]╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝<br />
O══════════════════════════════O<br />
[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@][#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼[#5:1]^[#0:0][@7:0]■[@#]☼☼ P0i and P0i-1. P1<br />
[#7:1]╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝ ╚╝<br />
</diagram><br />
Kogge-Stone Adder<br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a power to signal converter. The power to signal converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258092User:Green Sprite2021-06-06T22:55:47Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]<br />
[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
.<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
[#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.<br />
[%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]<br />
OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]<br />
[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]].<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a power to signal converter. The power to signal converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258091User:Green Sprite2021-06-06T22:41:46Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188][#]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]].<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.<br />
==Edge Detectors (Rising and Falling)==<br />
Rising edge detector design:<br />
<diagram fg=7:1><br />
╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗<br />
╚═════╝<br />
</diagram><br />
The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a power to signal converter. The power to signal converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.<br />
<br />
The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258085User:Green Sprite2021-06-06T05:01:55Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188][#]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]].<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258084User:Green Sprite2021-06-06T04:54:45Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
==Instructions==<br />
{|class="wikitable"<br />
|-<br />
|0x0<br />
|Halt.<br />
|-<br />
|0x1<br />
|Load memory address to A.<br />
|-<br />
|0x2<br />
|Copy A to B.<br />
|-<br />
|0x3<br />
|Copy A to C.<br />
|-<br />
|0x4<br />
|Copy A to PC if C is not 0.<br />
|-<br />
|0x5<br />
|Store A to memory address.<br />
|-<br />
|0x6<br />
|\---<br />
|-<br />
|0x7<br />
|\---<br />
|-<br />
|0x8<br />
|Add A + B. Write result to A.<br />
|-<br />
|0x9<br />
|Increment 1 to A.<br />
|-<br />
|0xA<br />
|Subtract A - B. Write result to A.<br />
|-<br />
|0xB<br />
|Decrement 1 from A.<br />
|-<br />
|0xC<br />
|Shift A left by given amount.<br />
|-<br />
|0xD<br />
|Shift A right by given amount.<br />
|-<br />
|0xE<br />
|Bitwise A and B. Write result to A.<br />
|-<br />
|0xF<br />
|Bitwise not A. Write result to A.<br />
|}<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188][#]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a power to signal converter.<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258083User:Green Sprite2021-06-06T04:38:41Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.<br />
==Registers==<br />
{| class="wikitable"<br />
|-<br />
|A<br />
|Main register, input of arithmetic operators and where the results are written.<br />
|-<br />
|B<br />
|Secondary register, most operations that need two inputs will use this register.<br />
|-<br />
|C<br />
|Conditional register, involved in low-level if statements.<br />
|-<br />
|PC<br />
|Program counter which keeps track of the memory address for the next instruction.<br />
|}<br />
<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188][#]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a power to signal converter.<br />
==Binary Decoder==<br />
I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=Repeater&diff=258082Repeater2021-06-06T04:16:50Z<p>Green Sprite: Changed old diagram tags to new ones ({{diagram}} to <diagram>). Now all diagram use the same format.</p>
<hr />
<div>{{Quality|Exceptional|11:56, 18 May 2015 (UTC)}}<br />
{{av}}<br />
{{Computing}}<br />
In ''Dwarf Fortress''*, a '''repeater''' is a device which creates a cyclic pattern of on and off signals. The simplest repeater design is a [[dwarf]] pulling a [[lever]] on [[repeat]]. However, numerous fully-automated designs are possible which can be made to operate at varying rates and linked to other systems for precise timing. Most repeaters use [[minecart]]s, fluids, or creatures to trigger [[pressure plate]]s cyclically.<br />
<br />
As a general warning, always have a way to turn off the repeater, and/or allow your dwarves later access for repairs or modifications.<br />
<br />
: (* In almost any other context, especially engineering or "technical" discussions, the term "repeater" refers to a signal re-transmitter, and what this article describes is generally called an "oscillator" or "clock generator".)<br />
<br />
===Lever repeater===<br />
A lever with a pull job on repeat provides the simplest repeating cycle. After taking the first job, one dwarf will typically continue to pull the lever until becoming [[Food|hungry]], thirsty, or tired, at which point another dwarf will take over. A lever repeater is generally fast (less than 100 ticks per cycle), with varying lengths of inactivity as dwarves switch out. Unfortunately, the cycle length cannot be modified, nor can the repeater be synchronized with other systems. The occasional periods of inactivity can also prove problematic in critical applications, though a [[vampire]] can be significantly more reliable than a group of living dwarves.<br />
<br />
===Traffic repeater===<br />
For low-priority tasks, a civilian-triggered [[pressure plate]] built in a hallway of the fortress can provide a simple oscillating signal automatically. The signal from such a repeater varies widely, though it can be adjusted somewhat by choosing hallways with more or less traffic. The lack of precision means that traffic repeaters are best utilized where a task needs to occur occasionally, but the timing is unimportant (such as triggering an [[atom smasher]] at the bottom of a garbage chute).<br />
<br />
===Wave repeater===<br />
A wave repeater is simply a wave traveling through a channel containing a pressure plate, as described in this [http://www.bay12forums.com/smf/index.php?topic=68659.0 forum post].<br />
<diagram fg=7:0><br />
╔══════╗ ╔══════╗<br />
║[#F0F]^[#].....║-->║[#0FF]777776[#]║<br />
╚══════╝ ╚══════╝<br />
</diagram><br />
<br />
A single 6/7 water tile flows through the channel, occasionally triggering a pressure plate set to trigger on 0-6/7 water. To get the right amount of water in it, it's simplest to fill it all the way, then designate it as a [[Activity_zone#Water_source|water source]] (and perhaps another location as a [[Activity_zone#Pit/pond|pond]]) until a dwarf takes away a single [[bucket]] full of water.<br />
<br />
As designed (5 tiles of non-triggering water, 1 tile of triggering water), this setup triggers rapidly, on par with the repeaters described below. Counter-intuitively, making it smaller or removing more water slows the action of the repeater because the pressure plate never gets a chance to recover from triggering, which takes 100 ticks. Unfortunately, liquids behave semi-randomly, which means the period of this repeater can vary, making it unsuitable for fine timing applications.<br />
<br />
Note about pond/pit filling the repeater. Pond/pits can only be filled to 6/7 so you will need to set the pressure plate accordingly to trigger on 0-5/7.<br />
<br />
It's possible to make a design that can be easily started and stopped, even one that conserves water, but such systems are complex, when the beauty of this design is its simplicity. If it needs to be stopped for maintenance, one is probably best off simply dropping another bucket of water in it.<br />
<br />
===Fluid logic repeater===<br />
The traditional repeater design is probably this [[fluid logic|fluid]]-based one, described on the [http://www.bay12forums.com/smf/index.php?topic=33563.msg495183#msg495183 forum] by [http://www.bay12forums.com/smf/index.php?action=profile;u=16168 AncientEnemy]):<br />
<br />
<diagram> [#1:1]≈≈≈≈≈[#] - infinite source of water<br />
═╗[#1:1]≈[#]╔═ - wall to channel out after construction<br />
╠[#7:0][@7:1]X[@#]╣ - shutoff floodgate (linked to exterior lever)<br />
║#║ - 1-tile drawbridge (linked to pressure plate)<br />
║[#5:1]^[#]┼ - pressure plate (set to 7-7 water), and access door <br />
╠[#7:0][@7:1]X[@#]╣ - floodgate (linked to pressure plate)<br />
╚═╝<br />
</diagram><br />
<br />
So long as the shutoff [[floodgate]] isn't closed, [[water]] from an infinite source flows on to the pressure plate, causing the raising [[bridge]] to block access to the water source and destroy water in the circuit, while the opening of the southern floodgate compensates for the space taken up by this bridge. This water destruction mechanic means that, unlike many fluid logic circuits, this repeater needs no drainage. The single pressure plate works both to regulate the repeater, and as output.<br />
<br />
This repeater toggles fairly slowly, about once every 300 steps, making it suitable for operating repeating bridges, floodgates, and [[Trap#Upright Spear/Spike|upright spikes]]. Off signals tend to follow on signals about 200 ticks later. As an added bonus, the southern wall can be removed and connected to a [[reservoir|cistern]] whose water level will be automatically maintained at a level between 3 and 4 deep-- perfect for [[swimmer|swimming]]!<br />
<br />
For an alternate water-based repeater, consider the design at [[User:SL/Logic_Gates#Repeater]] which demonstrates a two level, hybrid repeater.<br />
<br />
===Goblin repeater===<br />
Designs based on [[creature logic]] are also possible. The following example is compact, reliable, and fairly predictable.<br />
<br />
<diagram><br />
╔═╗ <br />
═══╝[#FF0]¢[#]╚══<br />
[#F00]p[#FF0]¢^¢[#00F]¢[#F0F][@00F]^[#00F][@]¢[#F00]p[#]<br />
══╗[#00F]¢[#]╔═══<br />
╚═╝<br />
</diagram><br />
<br />
A captured goblin placed between the two pressure plates drives this system in his attempts to reach map edge through paths {{Raw Tile|¢p|#F00|#000}}. {{Raw Tile|^|#FF0|#000}} is linked to all {{Raw Tile|¢|#FF0|#000}}, and {{Raw Tile|^|#F0F|#00F}} is linked to all {{Raw Tile|¢|#00F|#000}}, as well as to output. This gives the goblin a path away from his constrained tile every 100 ticks. Delays in picking up path tend to make it run a cycle every 250 ticks. with on and off signals separated by about 120 ticks. Its rate of repetition can be doubled by hooking both {{Raw Tile|^|#FFF|#000}} to output, although this leads to close placement of on and off signals.<br />
<br />
===Minecart repeater===<br />
<br />
In the simplest application, a hauler can guide a [[minecart]] across a pressure plate and around a circular track on a set schedule. A hauling route stop set to guide after X days has a fixed minimum interval (X days), but the maximum cycle time is somewhat variable (depending on how long it takes a hauler to accept the job and walk to the minecart). This type of repeater can be useful for triggering occasional time-insensitive events, like enabling a [[mist|mist generator]] for a few days every month.<br />
<br />
To remove the dwarf timing uncertainty, a [[Minecart#Roller|roller]] can propel the [[minecart]] around the circular track instead. Due to the fixed speed provided by rollers and the deterministic behaviour of minecarts, this type of minecart repeater provides a cycle with an absolutely constant repeat time. The exact period of such a powered repeater is relatively easy to regulate by choosing the operation speed of the roller, by adjusting the length of the track and by adding medium- and low-friction [[Minecart#Track stop|track stops]] to reduce movement speed. <br />
<br />
The [[Minecart#Impulse ramps|impulse ramp]] exploit allows for the design of completely autonomous minecart-based repeaters. Changing the length and friction of the route provides the ability to fine-tune the period of the repeater.<br />
<br />
This design uses a 7 by 8 by 3 Z-level footprint, and was used for upright spike traps. It was originally posted [http://www.bay12forums.com/smf/index.php?topic=154293.msg6643457#msg6643457 in this forum thread.]<br />
<br />
z z-1 z-2<br />
1234567890 1234567890 1234567890 <br />
wwwwwwwwww 1 wwwwwwwwww 1 wwwwwwwwww where<br />
wwwwwwwwww 2 wwwwwwwwww 2 wDDDDDDDDw w = unchanged wall<br />
wwwwwwwwww 3 wwwwwwwwww 3 wDwwwwwwDw D = dig prio 4<br />
wwwwwwwwww 4 wwwwwwwwww 4 wDwwwwwwDw h = channel prio 4<br />
wwwwwwwwww 5 wwwwwwwwww 5 wDwwwwwwDw H = channel prio 5<br />
wwwwwwwwww 6 wwwwwwwwww 6 wDwwwwwwDw <br />
wwwwwwwwww 7 wwwwwwwwww 7 wDwwwwwwDw <br />
wwwwwwhDhw 8 wwwwwhwwHw 8 wDDDDwwwww <br />
wwwwwwwwww 9 wwwwwwwwDw 9 wwwwwwwwww <br />
<br />
# Carve a track at all the 'D' tiles in the obvious direction.<br />
# Carve N/E impulse ramps at the three ramps (2 on Z - 2, one on Z - 1)<br />
# Place a hatch cover over the east chute on Z and define a track stop there (with a mine cart, of course). <br />
## Remove the default movement orders for the stop. <br />
## Hook the hatch to a start/stop lever. (not pictured)<br />
# Build a mine cart activated pressure plate anywhere on the flat track (i.e. not any ramp), for example, 2 tiles N of the drop chute starting the repeater.<br />
# Hook the pressure plate up to the focus of the repeater (spike traps, danger room, bridge, etc).<br />
# Clear out or forbid all the debris in the tunnel, or you run the risk of creating road kill as someone goes to pick it up.<br />
# Use the lever to start and stop the process.<br />
<br />
<br />
See [http://www.bay12forums.com/smf/index.php?topic=114695.0 this forum thread] for other designs tuned for bridge and upright spike traps.<br />
<br />
See [http://www.bay12forums.com/smf/index.php?topic=126154.0 this forum thread] for a super-compact design.<br />
<br />
Minecart repeaters can be calibrated to periods usable in the construction of clocks, like 200, 300 or 400 steps. Powered repeaters of this type will require nothing but a single roller and the power to run it, one pressure plate and a bit of space for the track. Repeaters using ramps to create perpetual motion don't need the roller or power but tend to be a bit more difficult to calibrate to useful periods and need additional infrastructure to stop their operation.<br />
<br />
Minecart repeaters can also be synchronized with other systems. Adding additional pressure plates to the tracks can allow a single repeater to provide multiple offset signals, and/or a [[Pressure_plate#Lightspeed_repeater|combined high-frequency signal]]. Alternatively, a pressure plate can trigger another independently-timed system.<br />
<br />
==Clock Generation==<br />
Although the law of big numbers means that, over large enough intervals, the abovementioned irregular repeaters (the fluid and goblin logic ones) can be used to run a clock, designs that generate perfect clock signals have been known for a while.<br />
<br />
This [[mechanical logic|mechanical]]-fluid hybrid repeater was the first proposed device to produce completely regular signals, at a frequency determined by the speed of pressure plate recovery. The basic design consists of 4 [[screw pump]]s and 4 pressure plates but other versions are possible, depending on the number of separate steps you need.<br />
<br />
<br />
<diagram bg=7:0 fg=7:0><br />
[#0:0]Level │Level │Level <br />
0 │-1 │-2<br />
──────┼──────┼──────<br />
│ │ <br />
[#6:1][@0:0]☼[@] [#0:0]│ [@0:0] [#2:1]÷[#2:0]÷ [@] [#0:0]│ [@0:0][#4:1]^[@] [@0:0][#2:1]^[@#] <br />
[@0:0][#1:1]☼[#]☼☼[#6:0]══[@][#0:0]│ [@0:0][#2:0]÷[@] [@0:0][#2:1]÷[@] [#0:0]│<br />
[@0:0][#]☼[#4:1]☼[@] [#0:0]│ [@0:0][#2:1]÷[@] [@0:0][#2:0]÷[@] [#0:0]│<br />
[@0:0][#2:1]☼[@] [#0:0]│ [@0:0] [#2:0]÷[#2:1]÷ [@] [#0:0]│ [@0:0][#6:1]^[@] [@0:0][#1:1]^[@#] <br />
[#0:0]│ [#0:0]│ <br />
</diagram><br />
{{Raw Tile|÷|#0f0|#000}}{{Raw Tile|÷|#008000|#000}} is a screw pump which pumps from the light side to the dark side. {{Raw Tile|^|#f00|#000}} is a pressure plate which disengages gear {{Raw Tile|☼|#f00|#000}} when water of depth 1-7 lands on it. The red, green, blue, and yellow pressure plates and gears are color coded only to show which is linked to which. In the game they'll all look like {{Raw Tile|^|#f0f|#000}} and {{Raw Tile|☼|#c0c0c0|#000}}. Building a pump after the gear which powers it or a gear after the pressure plate which disengages it will introduce a 1-step delay; so, depending on build order, the repeater might have a period between 400 and 408 steps. If the pumps, gears, and pressure plates are built in that order, then this system will repeat every 400 steps, exactly. Start the repeater by using a pond zone to dump 2 buckets of water onto any one of the plates.<br />
<br />
The device as depicted uses 47-62 power during operation, and requires 62 power for startup. Drive train to power may, of course, lead to higher requirements. Once the two units of water are introduced to the system, water is conserved perfectly.<br />
<br />
See [[User:MrFake/NStepCyclicRepeater]] for generalizable n-step clock generator instructions.<br />
<br />
[[User:Hash/SelfPoweredHaltableRepeater]] demonstrates clock generation with integrated water [[water_wheel#perpetual_motion|reactor]].<br />
<br />
[http://www.bay12games.com/forum/index.php?topic=34407.msg572324#msg572324 Forum thread] has more description and explanations.<br />
<br />
[http://mkv25.net/dfma/movie-1370-pump-basedautorepeater DFMA movie] shows the action of pump-based clock generation.<br />
<br />
===Delay===<br />
Clock generation is closely related to the concept of delay: making a signal reach a target a certain amount of time after it is created. Any non-mechanical circuit introduces delay in a signal-- the simplest form of delay is an identity gate. The clock signal generator described above is remarkable for introducing a consistent delay. Any consistent delay can be used for clock generation. Before the introduction of minecarts, there were three known consistent intervals in ''Dwarf Fortress'' with which to fashion a clock signal generator: the reset delay associated with a pressure plate sending a ''close'' signal; the rate with which a creature [[gravity|falls]]; and the amount of time that a screw pump will continue to pump after losing power. <br />
<br />
<br />
{{Category|Computing}}<br />
[[ru:Repeater]]</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258081User:Green Sprite2021-06-05T23:05:17Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.<br />
===Memory read===<br />
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[%186]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188] [%200][%188] [%200][%188] [%200][%188][#]<br />
</frame><br />
</diagram><br />
In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a power to signal converter.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258080User:Green Sprite2021-06-05T21:48:10Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off.<br />
===Memory read===<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
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[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#] [#7:0]OO[#][#6:0][%186][#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#] [#7:1][%200][%188][#] [#7:1][%200][%188][#] [#7:1][%200][%188][#]<br />
</frame><br />
</diagram></div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258068User:Green Sprite2021-06-05T06:26:07Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off.<br />
===Memory read===<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
<br />
<br />
<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO OO OO OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#] [#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
</frame><br />
</diagram></div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258067User:Green Sprite2021-06-05T06:20:59Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off.<br />
===Memory read===<br />
<diagram fg=6:0><br />
<frame type=level level=1><br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#7:0].<br />
. Z=1<br />
.[#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0]OO[#]<br />
[#5:1]^[#][#0:0][@7:0][%254][#@][#2:1][%15][#]<br />
[#7:1][%200][%188][#]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[%186] [%186] [%186] [%186] [%186] [%186] [%186] [%186]<br />
[#7:0].<br />
. Z=0<br />
.[#]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
</frame><br />
</diagram></div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258066User:Green Sprite2021-06-05T05:44:20Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off.<br />
===Memory read===<br />
<diagram fg=7:0><br />
<frame type=level level=1><br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
[#6:0][%186][#]<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
.<br />
. Z=1<br />
.<br />
[#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#]<br />
[#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#]<br />
</frame><br />
<frame type=level level=0><br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
.<br />
. Z=0<br />
.<br />
[#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#]<br />
[#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#]<br />
</frame><br />
</diagram></div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258065User:Green Sprite2021-06-05T03:49:21Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off.<br />
===Memory read===</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258064User:Green Sprite2021-06-05T01:38:41Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
===Single bit cell===<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
===Byte cell===<br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.<br />
===Memory write===<br />
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in the registry connects to the {{Raw Tile|☼|#0F0}} northern gear assembly, and also to the {{Raw Tile|☼|#080}} sourthern gear assembly. The northern gear assembly is inverted.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258063User:Green Sprite2021-06-05T00:46:30Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram><br />
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.</div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258062User:Green Sprite2021-06-05T00:42:37Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br><br />
Design for byte:<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
[#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#][#7:1][%186][#]O[#7:1][%210][#][#2:1][%15][#]<br />
[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O[#7:1][%208][#][#2:0][%15][#][#7:1][%186][#]O<br />
[%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#][%201][%187][#7:1][%208][#][#2:0][%15][#]<br />
[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O<br />
</diagram></div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258061User:Green Sprite2021-06-05T00:28:30Z<p>Green Sprite: </p>
<hr />
<div>=Dwarftel Core d1=<br />
==Memory Cell==<br />
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br />
Design for byte<br />
<diagram fg=7:0><br />
O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]<br />
[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]<br />
<br />
</diagram></div>Green Spritehttps://dwarffortresswiki.org/index.php?title=User:Green_Sprite&diff=258060User:Green Sprite2021-06-04T23:57:00Z<p>Green Sprite: Removed new page tag</p>
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<div></div>Green Spritehttps://dwarffortresswiki.org/index.php?title=Dwarf_Fortress_Wiki:Page_request/List&diff=258057Dwarf Fortress Wiki:Page request/List2021-06-04T23:46:45Z<p>Green Sprite: New page request</p>
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<div>{{page request header|List of page requests}}<br />
:''This is a '''list''' of page requests. See [[DF:PR|this page]] for assistance with requesting a new page.''<br />
== Recently created pages ==<br />
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== Article requests ==<br />
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*Request: I would like to create [[The Long Night]] and several associated articles [[The Long Night: Civilizations]], [[The Long Night: Creatures]], [[The Long Night: Materials]], [[The Long Night: Weapons]], and [[The Long Night: Armor]] to form a more easily navigated guide to the new features found in the mod of the same name. [[Special:Contributions/98.212.135.225|98.212.135.225]] 23:51, 1 September 2020 (UTC)<br />
** Since this is a mod, it should go under the mod namespace. I've created [[Mod:The Long Night]]; as it expands, I would suggest creating subpages like [[Mod:The Long Night/Creatures]]. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 01:25, 2 September 2020 (UTC)<br />
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* request: [[DF2014:Altar]] [[Special:Contributions/35.191.8.17|35.191.8.17]] 00:11, 17 February 2020 (UTC)<br />
** Done. DF also refers to these as "offering place"s in the {{k|b}} menu, but I didn't see existing pages where either of these were mentioned from a quick search. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 00:03, 30 June 2020 (UTC)<br />
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* Request: I would like to create [[DF2014:Messenger]] specifically with the information that they are assigned on the locations screen [[User:Keupo|Keupo]] ([[User talk:Keupo|talk]]) 06:56, 27 June 2018 (UTC)<br />
** You already have permission to do this since you've made 3 edits now. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 17:31, 27 June 2018 (UTC)<br />
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* Request: I would like to create [[Civilization/World_Info_menu]] [[User:Azeroth2b|Azeroth2b]] ([[User talk:Azeroth2b|talk]]) 18:33, 13 December 2017 (UTC)<br />
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* Request: I would like to create [[DF2014:Kisat Dur]] [[Special:Contributions/174.27.44.232|174.27.44.232]] 00:14, 31 July 2016 (UTC)<br />
** Done. [http://www.bay12forums.com/smf/index.php?topic=148015.0 Forum thread] for reference. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 02:09, 1 August 2016 (UTC)<br />
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* Request: [[DF2014:Reaction examples]] Simply copy the old page from v0.31 for more resources. Many old pages on modding haven't been pushed through versions even when they are still accurate. [[Special:Contributions/2606:A000:FD44:7A00:B58A:AB43:BD25:B51C|2606:A000:FD44:7A00:B58A:AB43:BD25:B51C]] 22:23, 28 March 2016 (UTC)Ryga_<br />
** Done.--[[User:Loci|Loci]] ([[User talk:Loci|talk]]) 19:47, 1 August 2016 (UTC)<br />
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* Request: I would like to create [[DF2014:Philosopher]] and [[DF2014:Sage]] because these are new scholar jobs in 42.xx [[User:Lead Cafe|Lead Cafe]] ([[User talk:Lead Cafe|talk]]) 22:33, 28 January 2016 (UTC)<br />
** Both are profession titles associated with scholars; I created them as redirects to [[DF2014:Scholar]].--[[User:Loci|Loci]] ([[User talk:Loci|talk]]) 04:08, 29 January 2016 (UTC)<br />
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*[[DF2014:Citizenship]] — here's one article on a new mechanic not currently covered by the wiki, we most definitely need to work on this. — [[Special:Contributions/94.19.200.59|94.19.200.59]] 20:39, 8 December 2015 (UTC)<br />
**Done. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 22:17, 4 January 2016 (UTC)<br />
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*[[Masterwork:Titanite]]: I can't find any information about Masterwork's Titanite, either from the wiki or Google. After mining some, I can only cut it like gems. Also need a to-do for this: build a crucible to determine if [[Masterwork:Titanium]] can be extracted from titanite. 1 Jan 2016<br />
**Done. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 22:17, 4 January 2016 (UTC)<br />
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*[[DF2014:Giant firefly]]: Just found one in my latest save of 0.42.05, realized a page didn't exist. [[User:ArcaneMusic|ArcaneMusic]] ([[User talk:ArcaneMusic|talk]]) 22:07, 19 January 2016 (UTC)<br />
** I just added a list of all the new creatures (probably contains some errors) on the talk pages of the [[graphic set]] and [[creature]] pages. Most of those probably need to be added as new pages too. In addition the page [[Back_bear_man]] should be deleted (mistyped b-L-ack bear man). In the future, it would be nice to have a script that simply goes through the creature raws and suggests new pages to be created for missing creature entries. [[User:CLA|CLA]] ([[User talk:CLA|talk]]) 15:12, 20 January 2016 (UTC)<br />
***The admins have bots that can create the pages automatically. Part of the hold-up is that the wiki's raws haven't been updated, so new creature pages aren't able to "autofill" with the appropriate details from the raws (and we prefer not to enter all that information manually).--[[User:Loci|Loci]] ([[User talk:Loci|talk]]) 20:38, 20 January 2016 (UTC)<br />
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*[[Masterwork:Drake]] The article is blank. Since these are a domestic animal that players can grab on embark, there should be some information about them for people new to the mod. [[User:Apollo Densin|Apollo Densin]] ([[User talk:Apollo Densin|talk]]) 02:00, 11 March 2019 (UTC)<br />
** Done.--[[User:Loci|Loci]] ([[User talk:Loci|talk]]) 23:50, 13 March 2019 (UTC)<br />
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*Version 0.47.1 added [[DF2014:Fort]], [[DF2014:Constructed creatures]], and perhaps [[DF2014:Intelligent undead]]. It also allows to [[DF2014:Mount]] creatures. A lot of other new features deserve their pages. Perhaps we should create a DF2020 version of pages.<br />
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== Talk page requests ==<br />
<!-- Add new requests directly below this line (remember to sign with ~~~~). Don't forget to save using the "Save page" button below! --><br />
I would like a talk page for [[DF2014:Bauxite]] and [[DF2014:Aluminum]]. [[User:Magic9mushroom|Magic9mushroom]] ([[User talk:Magic9mushroom|talk]]) 04:24, 17 August 2019 (UTC)<br />
:Done. -- [[User:Loci|Loci]] ([[User talk:Loci|talk]]) 18:58, 18 August 2019 (UTC)<br />
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Request: Talk page for [[DF2012:Repeater]] [[Special:Contributions/68.6.123.36|68.6.123.36]] 03:38, 25 March 2014 (UTC)<br />
:Done. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 03:44, 25 March 2014 (UTC)<br />
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Masterwork_Talk:Guildhall [[Special:Contributions/68.46.84.117|68.46.84.117]] 14:02, 20 October 2013 (UTC)<br />
:Done. --[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 15:01, 20 October 2013 (UTC)<br />
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Hello, would you be able to create a Talk page with the following question for me?:<br />
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"Do children born during fortress mode (or worldgen if you can find out) adopt the dieties of their friends/parents, or are they assigned a random diety? Is this with immediate effect from birth?<br />
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Thanks.<br />
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Josh"<br />
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Thank you! :)<br />
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Hello, I'd like to open another talk/discussion page for "Size" (http://dwarffortresswiki.org/index.php/DF2012:Size) with the following question:<br />
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Are there any combat benefits to SMALL dwarves?<br />
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On one of the pages for an older version of DF it notes that large creatures like elephants have a hard time landing a hit on small creatures like cavies. Would this alleged bonus to-dodge and/or penalty to-hit modifier translate in any meaningul way for smaller dwarves?<br />
:[[DF2012 talk:Size|Done]]. --[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 19:05, 1 January 2014 (UTC)<br />
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I'd like to open a talk page for [[DF2012_Talk:Relationships]] with the following note (two paragraphs):<br />
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The royalty section is inaccurate. I have a second-generation native-born dwarf in one of my fortresses who has a plentitude of aunts and uncles and listed maternal and paternal grandparents. I'm not sure why having those relationships is only noticed for royalty, but I think it's partially because shorter worlds mean smaller lineages and partially because most forts don't last long enough to see native-born children grow up, get married, and have children of their own. I really don't think there's any reason why extended family would be limited to royalty in any case.<br />
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Anyway, I added parents to the Types section, and also grandparents because I hadn't noticed the Royalty section. I'd add Aunts/Uncles but I'm not sure where they fall in on the list, and baby Sarvesh doesn't have any cousins yet. <br />
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Thank you! --[[User:Lielac|Lielac]] ([[User talk:Lielac|talk]]) 02:41, 24 January 2014 (UTC)<br />
:Done. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 03:37, 24 January 2014 (UTC)<br />
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Hello, I feel that [[DF2012:World_generation]] should cover what goes into history simulation, as it is obviously different to simulation in fortress mode.<br />
However, this is not a matter I am educated on. I would put this request on the page, but I cannot yet create a talk page.<br />
:Done. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 19:05, 22 April 2014 (UTC)<br />
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== User page requests ==<br />
<!-- Add new requests directly below this line (if you're NOT using {{upr|~~~}}, remember to sign with ~~~~). Don't forget to save using the "Save page" button below! --><br />
{{upr|[[User:DeathByBlue|DeathByBlue]] ([[User talk:DeathByBlue|talk]]) 02:31, 28 March 2020 (UTC)}}<br />
{{upr|[[User:Lead Cafe|Lead Cafe]] ([[User talk:Lead Cafe|talk]])}}<br />
{{upr|[[User:BillyJack|BillyJack]] ([[User talk:BillyJack|talk]])}}<br />
{{upr|[[User:BillyJack|Sandbox]] ([[User talk:BillyJack|talk]])}}<br />
{{upr|[[User:Theit8514|Theit8514]] ([[User talk:Theit8514|talk]])}}<br />
:Created. --[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 23:37, 30 June 2013 (UTC)<br />
{{upr|[[User:Mixtrak|Mixtrak]] ([[User talk:Mixtrak|talk]])}}<br />
{{upr|[[User:Green Sprite|Green Sprite]] ([[User talk:Green Sprite|talk]])}}<br />
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== Redirect requests ==<br />
<!-- Add new requests directly below this line (remember to sign with ~~~~). Don't forget to save using the "Save page" button below! --><br />
*[[DF2014:Fun]] to [[DF2014:Losing]]<br />
[[dfhack]], [[DFHack]] and [[DF2012:DFHack]] to [[Utility:DFHack]]. --[[User:Lurker|Lurker]] ([[User talk:Lurker|talk]]) 14:07, 7 August 2013 (UTC)<br />
:Done. --[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 17:48, 7 August 2013 (UTC)<br />
* Page "Taming" should redirect to "DF2012:Tame" [[User:Latias1290|Latias1290]] ([[User talk:Latias1290|talk]]) 18:02, 27 August 2013 (UTC)<br />
**[[DF2012:Tame]] is a redirect to [[DF2012:Animal trainer]]. Created [[Taming]] and [[DF2012:Taming]] as redirects. --[[User:Loci|Loci]] ([[User talk:Loci|talk]]) 19:33, 27 August 2013 (UTC)<br />
* Page "Gcs" should redirect to [[DF2014:Giant_cave_spider]]. [[Special:Contributions/199.60.104.18|199.60.104.18]] 19:00, 1 September 2015 (UTC)<br />
:Done. Just do it yourself next time. Just create the page and add "#REDIRECT" followed by a space and the link to the page.[[User:CLA|CLA]] ([[User talk:CLA|talk]]) 22:19, 1 September 2015 (UTC)<br />
::The reason this page exists is because anonymous users can't create pages. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 12:09, 4 September 2015 (UTC)<br />
:::Oh, that makes sense. Should have figured that out on my own.<br />
* [[DF2014:Combat log]] could redirect to [[DF2014:Reports]], I think it's the phrase new players will search for. [[User:Okdewit|Okdewit]] ([[User talk:Okdewit|talk]]) 18:58, 30 January 2016 (UTC)<br />
**Done. [[User:Jwoodward48|Jwoodward48]] ([[User talk:Jwoodward48|talk]]) 00:05, 2 March 2016 (UTC)<br />
* create redirect page "World Activation" and redirect to World_activities [[User:Untrustedlife|Untrustedlife]] ([[User talk:Untrustedlife|talk]]) 00:13, 26 July 2016 (UTC)<br />
-- Got it done [[User:Untrustedlife|Untrustedlife]] ([[User talk:Untrustedlife|talk]]) 00:16, 26 July 2016 (UTC)<br />
* Page [[DF2014:Guineahen]] and [[DF2014:Keet]] could redirect to [[DF2014:Guineafowl]] the same way [[DF2014:Guineacock]] does currently. [[Special:Contributions/2A01:C50E:D66A:5500:0:0:0:10|2A01:C50E:D66A:5500:0:0:0:10]] 17:43, 29 November 2017 (UTC)<br />
* Create redirect page for "Retire", "Unretiring", and "Retiring" and redirect to "Reclaim Fortress Mode" [[User:Benderdragon|Benderdragon]] ([[User talk:Benderdragon|talk]]) 16:21, 29 June 2020 (UTC)<br />
** Created [[Retire]]; [[Unretire]] already existed, and I'm hesitant to create redirects for the gerund forms - we don't have guidelines that specifically discourage them, but {{Rule|N}} and {{Rule|E}} are similar, and partial searches for "retir" or "unretir" should bring up the relevant pages in the search box anyway. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 00:12, 30 June 2020 (UTC)<br />
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== Other requests ==<br />
<!-- Add new requests directly below this line (remember to sign with ~~~~). Don't forget to save using the "Save page" button below! --><br />
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* Can someone include a discussion about how dwarfs choose which jobs/tasks to do if they have enabled multiple labors and there are jobs in multiple labors on the DF2012:Labor page? Is it based on which job is created first? Their skills / traits / attributes? Which labor they are highest ranked or their titled profession? This seems to be an issue in the LPs I've been watching early on when there are only the 7 starting dwarves, sometimes extending into the first migration. I know a solution is to deactivate other labors, or use burrows, but I'm still curious how it works. Thank you, [[Special:Contributions/108.243.77.185|108.243.77.185]] 03:08, 17 August 2013 (UTC)<br />
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* Hello. I wanted to know how to make the tiles uniform for the ground. I'm sure to have read somewhere once that it was possible to change the tiles to be all "." (I am currently searching for a Goblin Snatcher for a while now ^^). I searched for "ground" what has yielded me a link to above ground page. There was no link there. Could make one to the relevant article or indicate the settings to do please? [[Special:Contributions/31.164.176.33|31.164.176.33]] 20:04, 23 September 2013 (UTC)<br />
** Done: [[Ground]]. --[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 21:57, 23 September 2013 (UTC)<br />
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* Hi, im new and just want to start translation of the wiki into german. im really into this game and i guess i still could learn a shitload of new stuff by doing this. AND there would maybe be more players around if and when i/we translate. not every german is fluent in english. -f4nt4sy [[User:F4nt4sy|F4nt4sy]] ([[User talk:F4nt4sy|talk]]) 15:01, 1 March 2014 (UTC)<br />
:See [[DF:Centralized Discussion/Translating the wiki|here]]. It's been suggested before, but it's been hard to set something up on this wiki. &mdash;[[User:Lethosor|<span style="color:#074">Lethosor</span>]] ([[User talk:Lethosor|<span style="color:#092">talk</span>]]) 03:22, 2 March 2014 (UTC)<br />
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* I'd like to create a page under the centralized discussion for a proposal of subnamespaces for stuff like creatures, skills, etc. under a specific version. Stuff like DF2014:Rat becoming DF2014:Creatures:Rat. I'm not sure if the software allows this, but I thought I'd say it anyway.</div>Green Sprite