Editing User:Jjdorf/Logic Gates

I'll be using this as a spot to keep all my preferred logic designs in one spot.  Each design will specify the power requirements, build materials (excluding walls if constructing rather than digging), and build order, including the points when an input or output needs to be hooked up to things.  I consider gate technology in DF to be of two major types, Fluid Logic (FL), and Mechanical Logic (ML).  Borg logic, while interesting and certainly amusing, I believe to have too much of an impracticality in pathfinding cost and a lack of precision; Thus, I will generally disregard it until more intrepid scientists prove my biased assumptions incorrect.  For the most part, I will be using [[DF2010:Mechanical logic]] for my basic logic gates, due to the fact that I want to completely avoid the need for an infinite water source.  The exception to this restriction lies in two gates (so far), and these exceptions occur for a simply reason: they have variants which do not lose water.  Another design goal is the creation of mechanical logic gates that do not, in any way, use load gear trains to affect their operation.  I have verified that gears toggle, rather than set and reset, and that pre-toggling gears for the various gate designs also works, and as such, the mechanical logic designs below are far less complex and still 100% feasible to build, though the ones that require pre-toggling will cost one or two more mechanisms.
===NOTE===
A previous version of this page holds a fluid logic memory cell, derived from the one found on [[User:SL/Logic_Gates]], however I have further converted it, and since it uses gears, inverted pressure plate logic, and pre-toggling with one of the gears, I am listing only it in this and further versions of the page.
===Design Guidelines===
Because the natural state of a gear is to be engaged, the first guideline is that all logic inputs to a gate must be made while the input is logically TRUE.  This means that a lever intended to control an input must be flipped on before being linked to a logic gate, and it means that pressure plates must be designed to be on when the water level is under 4/7 or lower.  Exceptions for general purpose I/O can be made, but for logic gate design, this rule must be adhered to.

=Fluid/Hybrid Logic=
==FL Buffer/Rotation Sensor==
Modified slightly from: [[DF2010:Mechanical logic]]

    XXX       XXX
  S%>#D     .  .
    XXX       XXX
 
 XXXXXX    XXXXXX
 Do   X         X
 XXXXXX    XXXXXX

Both doors (D) are ordinarily forbidden under normal operation.  A water drain path is a good idea if maintenance is ever necessary on the bottom floor.  The mechanical input (S) provides the power to the pump.  Enough power must be available at this point to drive the pump (10 units) when the signal gear or axle is functioning.  The pressure plate (o) on the bottom layer is set to 0-3 water level.  The screw pump (%>) pumps away from the signal mechanism, towards a floor grate (#).
===Building===
* First, construct or dig the walls and floors.  If constructing, do NOT build floors at the empty space tiles (.), channel the same tiles if digging from the rock.
* Build the pressure plate on the bottom layer, then link it to whatever is needed.  Forbid the Bottom level door.  Build the grate.
* Build the screw pump, pumping toward the grate and away from the signal line direction.
* Designate a pond at the grate tile, filling the bottom layer full (all four tiles to 7/7 water).
* Hook the pump up to the signal mechanism.  Test with whatever logic is needed if desired.  The sensor is finished.
===Bill of Materials===
(Excluding the signal source and pressure plate linkage)
2 Doors
1 Mechanism
1 Corckscrew
1 Pipe Section
1 Block
1 Grate
===Inverter===
An inverter can be built with identical properties and build sequence by simply changing the pressure plate to trigger on 4-7 water.
===Hybrid===
Technically, this gate is designed for use solely in a hybrid environment, as the end result of a mechanical logic gear chain.  If intended to be used completely as Fluid logic, the source would be converted to a power input, moved to the side of the pump instead of over the source tile, a hatch would be placed over the source tile, defaulting to closed when off.
===Notes===
A Rotation sensor can also be considered a simple Buffer.  Buffers in actual electronics circuits are often used to increase the number of gates an output signal can be connected to, often by much more than the standard gate output can do.  Thus, I consider mechanical logic and fluid logic to be two different types of gates, and you use the gate that is best suited for the specific job.  Since fluid logic has a greater ''fan-out'' than mechanical logic, the fluid buffer can reset the power needed, since fundamentally, multiple mechanical gates '''can''' be connected together without issue until power runs out or you need to use load gear assemblies such as in an XOR or XNOR gate.
===TODO===
Verify that a signal gear or axle can be placed at (S) and still allow water to be pumped.  If this is not possible, adjust the design to put the gear one z-level above the pump, making sure to channel the floor to allow power transfer.  Construct and build a prototype and leave it run for a long time to verify the claim of no evaporation.  Dwarf Science!
===Pros/Cons===
The pressure plate requires 100 steps to switch off, but switches on immediately.  The sensor is water tight and should not evaporate under normal operation, allowing it to be disconnected from an infinite water source.
===How It Works===
When the source gear or axle is disabled, so will the pump be.  In this state, the water level in the bottom reservoir will be a constant 7/7, thus disabling the pressure plate (set to 0-3).  When the pump turns on, however, it pumps from the pressure plate tile constantly.  Thus will shift the water in that tile to the rear reservoir in the top level, keeping the plate clear of water, thus triggering the plate.  Since no tile of water will ever be less than 2/7 water at any time, no evaporation is possible (theoretically).
==HL (Hybrid Logic) RAM==
A Hybrid Logic Random Access Memory, basic cell structure:

  |
  *R         .
 
    XXX       XXX
  #%>#D     .  . 
    XXX       XXX
 
 XXXXXX    XXXXXX
 Do<%#D      . . 
 XXXXXX    XXXXXX
 
  | XXX       XXX
  *sX D       X  
    XXX       XXX

Each door (D) is a simple access door for internal maintenance.  Under normal circumstances, they should be forbidden entirely.  The grates (#) are there for completeness, ability to build the lower pump,  and safety when priming the cell with water.  If desired it could be omitted.  The pumps (%> and <%, pointing the direction of pumping, specifically, the % tile is walkable) are simple constructions, no special qualities.  Make them of whatever material is available.  The pressure plate (o) is set to detect only 0-3 water.  The walls (X) can be carved from rock or constructed as needed.  Power (|) is supplied through axles or gears.  The cell draws 21 units of power when connected with an axle, 25 when using a gear.  The set (S) gear and the reset (r) gear are both hooked up to the the data signal, though the set gear is pre-toggled.  Write Enabling should be handled by application of power (more on this in further designs...); specifically, if power is enabled, the cell will write, if it isn't, it will only be reading.
===Differences===
A major difference between this cell and other designs is simply that this cell is considered on when the cell reservoir is ''empty'' (i.e., the pressure plate has no water in its tile).  When the Data signal is received while powered, the set gear will be disengaged, and the reset gear will be engaged.  This means the bottom pump will be off and the top one will be on.  The cell will empty and the plate will trigger on.  When the data signal is lost while powered, the gears toggle and the pumps also toggle.  The top pump will stop pumping, and the bottom pump will activate.  The memory cell will fill the plate tile, turning off the plate's signal after 100 steps.  At any time power can be lost.  When this happens, the state of the memory cell will remain the same, since neither pump will continue to function.
===TODO===
Build and test this cell.  Verify that the pumps toggle immediately.
===Building===
* The first step is to construct the walls and floor, or carve the same.  If constructing, you should NOT build floors in the empty spaces (. on the right floor plan layout).  If digging from solid rock, channel open space at those places instead, placing the first grate at the right most spot on the middle layer to make channeling safe and easy.  You can build a wall instead of a door on the bottom layer.
* Build all doors, forbidding the bottom most door if you chose to build it.  Build the remaining grates and the pressure plate.  Build the screw pump on the middle z-level.
* Build the screw pump on the top z-level only after the first pump.  Meanwhile, fill the bottom most tile with water by designating a pond on the location of the grate in the middle layer.  Fill the bottom tile to 7 water, then remove the pond designation.
* Link the pressure plate to the output.  Build and link the set and reset gears, build a lever to pre-toggle the set gear, then dismantle the lever to reclaim two mechanisms.  Forbid the doors on the middle layer.
* Fill the middle layer with water from the grate tile on the top layer, until the open spot of the pump and the grate on the middle layer are both covered in 7 water, then remove the pond designation and forbid the top door.
* Build the power linkage.
===Bill of Materials===
(Excluding power source gear or axle and data source links)
3-4 Doors
2 Corkscrews
2 Pipe Sections
2 Blocks
3 Grates
8 Mechanisms (5 for gear assemblies, 1 for pre-toggling, 2 for linking the pressure plate)
2 Additional Mechanisms which are then recovered
===Maintenance===
You can adjust the connections of the gears as well as the pressure plate as needed.  The pressure plate is the only potentially submerged location in the cell, so pre-clearing the cell before maintenance is a good idea.
===Notes===
This cell does not have any "circuitry" to disable or enable the output of the cell based on addressing concerns, so if you add this to an addressable memory system, that gearing will be needed.  It should be, simply, an addition of another gear before a rotation sensor.
===Pros/Cons===
Similar to the FL RAM cell, but without the race condition from setting and resetting at the same time.  Just as fast and water efficient as the FL RAM cell, as well as being easier to maintain if it is discovered that gears were incorrectly built or linked.
===How It Works===
At its starting state, the pressure plate tile has no water, and thus the output of the cell is off, or 0.  The set gear is pre-toggled.  When the set/reset gears get their signal, the flip semantics, causing the set to be enabled and the reset to turn off.  This causes the middle pump to run, filling the cell reservoir to 7/7, while the top pump is off, leaving the cell reservoir filled.  The plate triggers and the memory cell is effectively on, or 1.  Power to both pumps can drop at this time and the output remains the same.  The rear reservoir now contains 7/7 at the lowest tile, and 3/7 and 4/7 fluctuating in the second layer, over the hatch and the walkable portion of the pump.  The water in the cell reservoir cannot drain, and will not be pumped out.  If power remains and the data signal toggles again, the set/reset gears will swap again, causing the cell to empty, and triggering the pressure plate off after 100-steps.  Again, if power is lost after the cell is emptied, the memory will still read out without problems.  If the set/reset gears toggle while power is out, no change occurs.  This allows Power to be an effective Write enable signal.  The exact order of data signal change followed by write enable is not crucial, as long as both occur at the same time to cause a write to the cell.
===Electrical Similarities===
This memory cell design is almost identical to a standard D Flip-Flop circuit.  The differences are similar to the FL RAM cell and an RS Flip-Flop.

=Pre-Toggle Mechanical Logic Gates (PTML Gates)=
In light of the fact that Gears are toggled, not set or unset, I am looking into the concept of more efficient designs for certain mechanical gates.  The result is that the excessive load gear trains for certain gates can be eliminated, providing quantifiable power usage per gate, and making power source designs less complicated.  For completeness I will also show the designs for unaffected gates.  In the diagrams for Mechanical Logic gates, power sources and outputs may be gears, axles, or direct connections to a pump in the case of outputs.  Sometimes it will be necessary for the power to be an extra gear.  Power train and output train design are secondary and much simpler concerns.  In the diagrams, capital letters indicate a normally constructed gear assembly, while miniscule letters indicate a gear assembly that is toggled once after construction with a lever.  All input links to a gear should be done in the logical off mode, such as with a newly built lever, or with a 7-7 water pressure plate with no water resting on it.

==ML Buffer==
Essentially this is an identity gate.  It is the simplest ML gate possible, using at least one gear assembly to transfer power.  It is, essentially, the reverse of the rotation sensor, taking a linked signal and converting it to P - 5 power.

 PIO

Power is supplied (P), and if the input gear is functional (I), then the power, less 5 for the input gear, will be transferred to the output (O). Construction is simple, make the gear assembly and link to the signal.
===Bill of Materials===
For the gate itself, just one mechanism.  Linking signals is never counted in BoM.

==ML Inverter (NOT)==
This is similar to an identity gate. It is even constructed in a similar fashion, though you must also add a lever and pre-toggle the Input gear.

 PiO

Here, Power is supplied (P), and if the input gear is functional (i), then the power, less 5 for the input gear, is transferred to the output (O).  Construction is simple, make the gear assembly and a lever.  Link the gear assembly to the input signal, the lever to the gear, then flip the lever once.  Optionally destroy the lever to recover two mechanisms.
===Bill of Materials===
2 Mechanisms
2 Additional Mechanisms which are then recovered

==ML AND Gate==
Much like an ML Buffer gate.  Two gears instead of one, and both must be active to function.

 PABO

Power is supplied (P), and if both input gears are functional (A & B), then the power, less 10 for the gears, will be transferred to the output (O).  Construction is simple, make the gear assemblies and link them to their respective signals.
===Bill of Materials===
2 Mechanisms
===Equivalence to a Tri-State Buffer===
With mechanical logic, the ML AND gate is equivalent to a Tri-State Buffer.  Namely, Mechanical Logic operates on the principle that a 0 value is the same as high impedance (no connection), while a 1 is a connection.  Thus, the truth table for an AND gate and a Tri-State Buffer, when 0 = Z (electronics details left out), are identical.  The Tri-State Buffer makes running a data bus possible.
===ML Multi-Input AND Bar/Stack===
The AND gate can be extended to multiple inputs by simply adding gears.  All gears need to be active in order for power to transfer.  Power cost will be the number of gears times 5 whenever the system is on.
==ML OR Gate==
Slightly more complex than the preceding ML gates, but still relatively easy.  Again, there are two inputs.  However, only one needs to be active for the result to be true.

 PA
 BO

Essentially, this is two separate identity paths from power to output.  As long as the power is available, either one can provide the needed power to output.  Power is supplied (P), and if either input gears are functional (A & B), then the power, less up to 10 for the gears, will be transferred to the output (O).  Construction is simple, make the gear assemblies and link them to their respective inputs.  Of particular importance is the fact that this gate can potentially be constructed one tile wide and two z-levels high, if the top layer is channeled out and the bottom layer is built first for safety reasons.
===Bill of Materials===
2 Mechanisms
Linking to a power or signal train may require additional gear assemblies, however.  Only a pump or a gear assembly can exist in the P and O spots.
===ML Multi-Input OR Bar/Stack===
Depending on the number of inputs desired, a multi-input OR gate can be constructed in a bar (horizontal) or stack (vertical).  For simplicity, I will diagram the bar method.  Converting it to a stack merely involves rotating it to stand on end.

 PPP
 ABC

 DEF
 OOO

The top level consists of three power gears, each connected to the mechanical power source, and three different inputs.  The bottom level consists of three more inputs, and three output gears, at least one of which must connect to a rotation sensor or the next logical gate in the line.  The power cost of a large input OR Bar will be the cost of running each power and output gear, as well as the cost of from 1 to all of the input gears.  A three input OR gate will require 7 mechanisms, 2 for power, 2 for output, and three input gears, and thus can cost anywhere from 25 to 35 power.  Obviously, the maximum power that can ever be drawn from such a gate is the number of gears times 5.

==ML NOR Gate==
Taking advantage of the ability to pre-toggle gears, a simple NOR gate can be constructed with almost no difficulty.

 PabO

Power is supplied (P), and if both input gears are functional (a & b), then the power, less 10 for the gears, will be transferred to the output (O).  Construction is mild, make the gear assemblies, construct two levers, link the levers to the gears, flip both levers, optionally dismantle the levers to recover mechanisms, then link the inputs to their sources.  It works as a NOR gate because we invert the inputs.
===Bill of Materials===
4 Mechanisms
4 Additional Mechanisms which are then recovered

==ML NAND Gate==
Again, taking advantage of the ability to pre-toggle gears, we can build a NAND gate without the need for a load gear train to overload power.

 Pa
 bO

Power is supplied (P), and if both input gears are functional (a & b), then the power, less up to 10 for the gears, will be transferred to the output (O).  Construction is mild, following the same build order as for a NOR gate, though the layout is different.  As with the NOR gate, it works because of the pre-toggled gears.  Of particular importance is the fact that this gate can potentially be constructed one tile wide and two z-levels high, if the top layer is channeled out and the bottom layer is built first for safety reasons.
===Bill of Materials===
4 Mechanisms
4 Additional Mechanisms which are then recovered
Linking to a power or signal train may require additional gear assemblies, however.  Only a pump or a gear assembly can exist in the P and O spots.

==ML XOR Gate==
A variant suggested by Dorf3000 from the Forums gives this XOR gate, which costs minimal power to run and is relatively simple to construct.

 PiO

The difference is that '''both''' the A & B inputs are linked up to the same single input gear.  I have tested with a synchronized pump system that two toggle signals occurring at the same time are treated as two separate toggles, and thus cancel out, as should be.  Of particular note is that this option is as power and space efficient as a simple NOT or Buffer gate.  Building is easy; build the input gear assembly, build a lever, link the lever to the gear, flip the lever then dismantle it, then link the inputs to the gear, ensuring that the input links are active, as per PTML design guidelines.
===Bill of Materials===
2 Mechanisms
2 Additional Mechanisms which are then recovered

==ML Full 1-bit Adder==
As designed on my forum posts, a 1-bit full feature adder "chip" can be built from combined logic gates.  This adder takes as input three single bit numbers, which are added together to produce two outputs, a result and a carry.

 OIPAB
   ZxC

Power (P) is provided, and must be a gear.  The outputs (O & C) are most likely to be direct connections to FL Buffers.  Input gears are the complicated part.  Each input signal, A, B, and Z, are the three single bit inputs.  Z is what is commonly known as the Carry input.  The gears labeled A, B, and Z are standard non-pre-toggled gears linked to these signals.  The two other gears use combinations of these inputs to produce the correct results.  The first, x, is a pre-toggled gear linked to A and B signals.  The second, I, is a non-pre-toggled gear linked to all three input signals.  This last gear is known as a three input XOR gate, and is active when an odd number of inputs are true.

The power cost of this gear train, including the P gear, but not addition power train, nor the output trains, costs exactly 30 power.  It will take 7 mechanisms to build, excluding the cost of linking input signals (which by my convention, is included in the cost of Fluid memory and buffer gates).

==DPROM==
Dwarf Programmable Read Only Memory, is quite simple.  It is a lever, flipped on before linking, as per PTML design guidelines.  Its special nature comes when a bank of 8 are hooked up to a data bus like any other pressure plate and addressing scheme.  (More on that later)
=Data Bus=
The data bus in a computing system needs a way to select one device on the bus to write to the bus, while all other portions of the bus are only allowed to read from the bus.  In Mechanical Logic, this isn't particularly feasible, since power limitations are very likely.  Instead a data bus will benefit from having both a device writer select and a device reader select signal set.  Depending on the number of devices allowed on the bus, this may be multiple communication channels (axles).

A connection spot to the bus will be a row of gears; specifically: 8 bits of data, however many bits of addressing are required by the bus, and perhaps a power supply.  It is my belief that power should be supplied conditionally to devices on the bus, if only to limit the number of Dwarven Water Reactor Systems needed by a computer, or whatever other method of powering is chosen.  Thus, a device should operate on the assumption that if it is not selected as the Write or Read target, it should shut off.  Essentially, the signal for reading or writing can be used in an OR gate to also provide device power.

I have more research to do in the design of a data bus, and some decisions to make regarding whether CPU internals should be part of the main system bus or simply hardwired within the CPU itself.  I suspect that some of the nature of the CPU will be easier if all devices are on one bus, though this depends on the number of bus devices.