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Editing User:Jjdorf/Logic Gates
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2 Mechanisms | 2 Mechanisms | ||
2 Additional Mechanisms which are then recovered | 2 Additional Mechanisms which are then recovered | ||
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− | + | ==ML Full 1-bit Adder== | |
− | + | As designed on my forum posts, a 1-bit full feature adder "chip" can be built from combined logic gates. This adder takes as input three single bit numbers, which are added together to produce two outputs, a result and a carry. | |
− | + | OIPAB | |
+ | ZxC | ||
− | + | Power (P) is provided, and must be a gear. The outputs (O & C) are most likely to be direct connections to FL Buffers. Input gears are the complicated part. Each input signal, A, B, and Z, are the three single bit inputs. Z is what is commonly known as the Carry input. The gears labeled A, B, and Z are standard non-pre-toggled gears linked to these signals. The two other gears use combinations of these inputs to produce the correct results. The first, x, is a pre-toggled gear linked to A and B signals. The second, I, is a non-pre-toggled gear linked to all three input signals. This last gear is known as a three input XOR gate, and is active when an odd number of inputs are true. | |
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− | + | The power cost of this gear train, including the P gear, but not addition power train, nor the output trains, costs exactly 30 power. It will take 7 mechanisms to build, excluding the cost of linking input signals (which by my convention, is included in the cost of Fluid memory and buffer gates). | |
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==DPROM== | ==DPROM== |