User:Jjdorf/TODO

• Test the rotation sensor, especially the possibility to power it from the source end of the screw pump.
• Design a Hybrid Logic (HL) Memory Cell, duplicating the D Flip-Flop semantics, specifically, a data line and a clock line instead of SET and RESET.
• For completeness go through and build all of the mechanical logic gates, verifying that each of them work. Test Dorf3000's XOR variant first, specifically the synchronized signal question, and if it works, skip the original variant for XOR. Of particular interest is whether gears properly toggle.
• Other designs such as a design which safely transfers power from z=0 to z=1, allowing connection of one gate to another that requires input on the top level.
• After verifying the D Flip-Flop cell is functional, design a Byte of HL memory, including power supply. This will also a Write Enable (WE) connection. The easiest way to do this is to only enable power to the pumps on a write enable.
• Design (Hah!) and diagram DPROM, Dorf Programmable Read Only Memory, i.e. a bank of levers. The design needs are simple enough, but will be useful when a full design for addressable memory comes into play.
• Design a General Purpose Input (GPI) cell. Ideally, this will simply be a plain FL buffer gate, with the signal gear being the gear that gets modified if the GPI connection needs to be changed, rather than pressure plate in the system, which would be dedicated entirely to the memory system.
• Design a General Purpose Output (GPO) cell. Ideally, this should simply be a plain HL Memory Cell combined with a buffer. The cell, in addition to being linked to the memory system, will also drive the buffer. The output of the buffer can be re-purposed for different outputs somewhat easier, disregarding any potential water issues. Proper Maintenance of the GPO buffer would involve writing a quick little program to turn the cell on, then applying it and going to make the change. While the buffer is on the pressure plate should be fully accessible.
• Design a demultiplexer/decoder circuit, taking a 3-bit binary input code and converting it into a set of gears, only one of which will be functional at once. This will be used for an addressing scheme.
• Design an 8-byte Addressable memory chip, including HL memory cells, 8-bit data inputs, 8-bit outputs, 3-bit address input, chip select input, Read enable and Write enable inputs, and, of course, the required power supply to run the chip. For the (hopefully) far future when Dwarven Water Reactors and other perpetual motion devices no longer work... explain how much power draw the chip takes. This will also help if a more compact memory block is to be built from this design, such as say... a block of 64 bytes.