Editing User:Jong/Dwarven Computer

== Notes ==

== Notes ==

Toggled gear assemblies are designed as though they are off in when untriggered. However they are constructed in the on position. This means that you need to build and link a lever to toggle it to the off state.

Toggled gear assemblies are designed as though they are off in when untriggered. However they are constructed in the on position. This means that you need to build and link a lever to toggle it to the off state.

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!width="40"|O

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The plate could be set to trigger at a lower threshold, which would slightly slow down response time, or a door could be used instead of a hatch and the unit extended by one tile to provide space for the drain. This would have the downside of destroying some water after every write operation.

The plate could be set to trigger at a lower threshold, which would slightly slow down response time, or a door could be used instead of a hatch and the unit extended by one tile to provide space for the drain. This would have the downside of destroying some water after every write operation.

8-bit words need 8-bit registers. Fortunately this just means stacking 8 memory units up and making sure they receive the same read/write signals.

8-bit words need 8-bit registers. Fortunately this just means stacking 8 memory units up and making sure they receive the same read/write signals.

The lines in the diagram don't actually represent physical connections but imaginary ones. After all, the write signal must be sent remotely.

The lines in the diagram don't actually represent physical connections but imaginary ones. After all, the write signal must be sent remotely.

Not all registers in the computer are 8 bit registers. For example the memory address register is 5 bits.

Not all registers in the computer are 8 bit registers. For example the memory address register is 5 bits.

Since there are only 5 bits of address space, I only need 256 memory cells. It should be fine if I don't use complicated column and row addressing schemes. I shall simply have 32 8-bit registers sticking somewhere. In order for the memory unit to work, I need a decoder to change the 5-bit address into 32 outputs. This will enable the memory unit to read and write from any register. I guess this makes it random access memory.

Since there are only 5 bits of address space, I only need 256 memory cells. It should be fine if I don't use complicated column and row addressing schemes. I shall simply have 32 8-bit registers sticking somewhere. In order for the memory unit to work, I need a decoder to change the 5-bit address into 32 outputs. This will enable the memory unit to read and write from any register. I guess this makes it random access memory.

This type of decoder is called an n to 2^n decoder, since it converts n inputs into 2^n outputs, in this case 5 to 32(2^5).

This type of decoder is called an n to 2^n decoder, since it converts n inputs into 2^n outputs, in this case 5 to 32(2^5).

Schematically this arrangement looks like this:

Schematically this arrangement looks like this:

Which is just some sort of tree diagram. I can easily expand this to n=5 which is what I want.

Which is just some sort of tree diagram. I can easily expand this to n=5 which is what I want.

I drew this diagram in rectangular form so that I can better see how to construct the decoder. The outputs of the decoder will be in a 4x8 grid. Since the output units are longer in one direction than the other, I will align their long axis along the short axis of the diagram. It is probably best to place all the mechanisms for the decoder in the level above the outputs.

I drew this diagram in rectangular form so that I can better see how to construct the decoder. The outputs of the decoder will be in a 4x8 grid. Since the output units are longer in one direction than the other, I will align their long axis along the short axis of the diagram. It is probably best to place all the mechanisms for the decoder in the level above the outputs.

The registers in the memory unit need some modification to work correctly. Only the register indicated in the memory address register ought to respond to read write signals. Therefore each of the 32 registers needs to be connected to one of the outputs from the decoder.

The registers in the memory unit need some modification to work correctly. Only the register indicated in the memory address register ought to respond to read write signals. Therefore each of the 32 registers needs to be connected to one of the outputs from the decoder.

It may be possible to wire the decoder directly to the power supply of the memory, which would remove the need for an output device.  

It may be possible to wire the decoder directly to the power supply of the memory, which would remove the need for an output device.  

Right, I based the design of the memory unit off a java applet simulator I found on the Internet.  

Right, I based the design of the memory unit off a java applet simulator I found on the Internet.  

What this diagram is supposed to illustrate is that ALL the memory cells are linked to respond to the same read-out signal and the same write-in signal. Similarly, all the corresponding cells respond to same input, and all output to the same place. However, they will do none of these things unless they get a signal from the decoder, and only one register will get the signal as indicated in the memory address register.  

What this diagram is supposed to illustrate is that ALL the memory cells are linked to respond to the same read-out signal and the same write-in signal. Similarly, all the corresponding cells respond to same input, and all output to the same place. However, they will do none of these things unless they get a signal from the decoder, and only one register will get the signal as indicated in the memory address register.  

Now the input and output buffers shown here may not be in the final blueprints, depending on the design of the rest of the computer.

Now the input and output buffers shown here may not be in the final blueprints, depending on the design of the rest of the computer.

The machine language is the set of instructions the computer will be able to execute. What these instructions are will define the design of the remaining components. For example, the Arithmetic Logic Unit needs to be able to perform the various operations listed in these instructions.

The machine language is the set of instructions the computer will be able to execute. What these instructions are will define the design of the remaining components. For example, the Arithmetic Logic Unit needs to be able to perform the various operations listed in these instructions.

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Now I know that the ALU needs to be able to perform 4 functions: Add, subtract, shift left and shift right. The unit needs to do one of these functions based on one of 4 input signals it may receive.

Now I know that the ALU needs to be able to perform 4 functions: Add, subtract, shift left and shift right. The unit needs to do one of these functions based on one of 4 input signals it may receive.

The ALU will receive 2 8-bit inputs and produce 1 8-bit output. It will require 3 systems, the adder-subtractor, bitshift left and bitshift right. These systems would be integrated to form the ALU.

The ALU will receive 2 8-bit inputs and produce 1 8-bit output. It will require 3 systems, the adder-subtractor, bitshift left and bitshift right. These systems would be integrated to form the ALU.

While there are existing dwarven adder designs out there, they do not come with schematics detailing the links between their components. Therefore I feel the need to design from scratch.

While there are existing dwarven adder designs out there, they do not come with schematics detailing the links between their components. Therefore I feel the need to design from scratch.

I believe this design uses the minimum number of gear assemblies, although I am not sure.

I believe this design uses the minimum number of gear assemblies, although I am not sure.

In order for an adder to work properly, it must also receive the carry bit in addition to the 2 inputs. Ultimately, even the first adder in the final adder-subtracter must be able to receive a carry bit to operate successfully, which is why I didn't draw up a full plan for the half adder.

In order for an adder to work properly, it must also receive the carry bit in addition to the 2 inputs. Ultimately, even the first adder in the final adder-subtracter must be able to receive a carry bit to operate successfully, which is why I didn't draw up a full plan for the half adder.

The above diagram details a hypothetical implementation for a full adder. The ```s represent the shadow of the mechanisms above and below the level. The left power sensor produces the output signal while the right power sensor produces the carry signal to be relayed to the next adder. The total footprint of the unit is 6x9. In an array, the units can overlap one tile so the total footprint of an 8-bit adder would be 41x9. Maximum operational power draw is 131x8(1048) units of power.

The above diagram details a hypothetical implementation for a full adder. The ```s represent the shadow of the mechanisms above and below the level. The left power sensor produces the output signal while the right power sensor produces the carry signal to be relayed to the next adder. The total footprint of the unit is 6x9. In an array, the units can overlap one tile so the total footprint of an 8-bit adder would be 41x9. Maximum operational power draw is 131x8(1048) units of power.

In order to build a full 8-bit adder-subtracter, all you need to do is to stack up 8 full adders next to each other and ensure that all the gears have been linked to the appropriate plates.

In order to build a full 8-bit adder-subtracter, all you need to do is to stack up 8 full adders next to each other and ensure that all the gears have been linked to the appropriate plates.

Now to get the adder-subtracter to subtract, all you have to do is to link up every single A and a (or B and b) gear assembly to the pressure plate sending the subtract signal. When the signal is sent, all the gears linked to a register will toggle. This will have the effect of inverting whatever input the register is sending. Finally the signal also needs to activate the carry in gears in the first adder, which will have the effect of adding 1 to the resulting sum (difference), giving the correct answer in two's complement representation.

Now to get the adder-subtracter to subtract, all you have to do is to link up every single A and a (or B and b) gear assembly to the pressure plate sending the subtract signal. When the signal is sent, all the gears linked to a register will toggle. This will have the effect of inverting whatever input the register is sending. Finally the signal also needs to activate the carry in gears in the first adder, which will have the effect of adding 1 to the resulting sum (difference), giving the correct answer in two's complement representation.

I did some research into carry-look-ahead adders to see if it was worth implementing. Carry-look-ahead adders are faster than ripple-carry adders as ripple carry adders have to wait for the carry bit to 'ripple' through the chain of adders before getting the correct result. This is most significant for users of fluid logic, as fluid logic adders need to wait n*100 steps (n being the number of bits) for the carry to ripple all the way to the end. (Floodgates and bridges have a 100 step delay before activating or deactivating)

I did some research into carry-look-ahead adders to see if it was worth implementing. Carry-look-ahead adders are faster than ripple-carry adders as ripple carry adders have to wait for the carry bit to 'ripple' through the chain of adders before getting the correct result. This is most significant for users of fluid logic, as fluid logic adders need to wait n*100 steps (n being the number of bits) for the carry to ripple all the way to the end. (Floodgates and bridges have a 100 step delay before activating or deactivating)

Firstly, looking at the carry-out circuit for the full adder, I see that not only can it exist independently from the sum circuit, the C gear is directly attached to the power source. I can take advantage of this by separating the carry bit calculation circuits from the adder and attaching them to each other like so.  

Firstly, looking at the carry-out circuit for the full adder, I see that not only can it exist independently from the sum circuit, the C gear is directly attached to the power source. I can take advantage of this by separating the carry bit calculation circuits from the adder and attaching them to each other like so.  

Then for the summing part of the adder, I simply build only the output circuit, which I can now simplify like this

Then for the summing part of the adder, I simply build only the output circuit, which I can now simplify like this

Since this system is superior in all ways to the ripple-carry system, this will be the one going into the final dwarven computer.

Since this system is superior in all ways to the ripple-carry system, this will be the one going into the final dwarven computer.

Setting up a bitshifting operation is relatively simple. I simply wire the inputs directly into slightly different outputs as illustrated in the following diagrams (source: Wikipedia http://en.wikipedia.org/wiki/Bitwise_operation#Arithmetic_shift).

Setting up a bitshifting operation is relatively simple. I simply wire the inputs directly into slightly different outputs as illustrated in the following diagrams (source: Wikipedia http://en.wikipedia.org/wiki/Bitwise_operation#Arithmetic_shift).

Ideally all these operations would be linked into the same bank of output buffers in the assembled ALU, which will be the subject of the next section.

Ideally all these operations would be linked into the same bank of output buffers in the assembled ALU, which will be the subject of the next section.

This diagram illustrates the various signals moving around the ALU. I decided that I ought to dragoon the ALU into incrementing the program counter as well, but I'm not sure whether that will work or not. We'll see in the later sections.

This diagram illustrates the various signals moving around the ALU. I decided that I ought to dragoon the ALU into incrementing the program counter as well, but I'm not sure whether that will work or not. We'll see in the later sections.

Adding a multiplexer onto the output circuit would require an additional z-level if the tiling efficiency is to be maintained.  

Adding a multiplexer onto the output circuit would require an additional z-level if the tiling efficiency is to be maintained.  

This diagram illustrates a hypothetical implementation of the multiplexer, as well as the bitshifting logic. I don't think I need a support axle on z+2 as it should be supported by O1.

This diagram illustrates a hypothetical implementation of the multiplexer, as well as the bitshifting logic. I don't think I need a support axle on z+2 as it should be supported by O1.

I've decided to ditch the plan for a bus, which would have been the conduit for data transfers between registers throughout the computer. Initially there were 2 methods, one had a output buffer attached to the end of the bus while the other the bus directly supplied power to the inputs of the appropriate registers.  

I've decided to ditch the plan for a bus, which would have been the conduit for data transfers between registers throughout the computer. Initially there were 2 methods, one had a output buffer attached to the end of the bus while the other the bus directly supplied power to the inputs of the appropriate registers.  

Method 2 would not work on memory cells that used an active pump for bit-clearing. Method 1 would have worked but the output buffers had to be overwritten every step and that could cause cascading delays throughout the computer. Since this computer is relatively simple, I opted for hard wiring everything instead.

Method 2 would not work on memory cells that used an active pump for bit-clearing. Method 1 would have worked but the output buffers had to be overwritten every step and that could cause cascading delays throughout the computer. Since this computer is relatively simple, I opted for hard wiring everything instead.

This diagram illustrates the data transfers that occur throughout the computer. The red arrows depict confirmed hard-wired connections, while the blue arrows would have been routed through a bus. I've decide AR1 is superfluous so I got rid of it. As you can see, each register has at most 2 inputs or 2 outputs going through the bus, so hardwiring is feasible.

This diagram illustrates the data transfers that occur throughout the computer. The red arrows depict confirmed hard-wired connections, while the blue arrows would have been routed through a bus. I've decide AR1 is superfluous so I got rid of it. As you can see, each register has at most 2 inputs or 2 outputs going through the bus, so hardwiring is feasible.

Before the computer can execute its instructions, it needs to perform some operations first.

Before the computer can execute its instructions, it needs to perform some operations first.

There needs to be a 100 step delay from the time a memory cell is written (or dumped, if it is pre-dumped) and when it is read, or it may cause cascading delays. The writing process is practically instantaneous, but 100 steps are needed before the correct result can be read if the memory was not cleared to begin with. Of course this point is entirely moot if the computer is running automatically, in which case every step will last at least 100 steps anyway and the prime consideration is to ensure that every step can be performed in 100 steps.

There needs to be a 100 step delay from the time a memory cell is written (or dumped, if it is pre-dumped) and when it is read, or it may cause cascading delays. The writing process is practically instantaneous, but 100 steps are needed before the correct result can be read if the memory was not cleared to begin with. Of course this point is entirely moot if the computer is running automatically, in which case every step will last at least 100 steps anyway and the prime consideration is to ensure that every step can be performed in 100 steps.

A typical mechanical oscillator is unsatisfactory because it will usually be sending out 2 on signals at once, one from the pressure plate the water is on and the other from the pressure plate waiting to reset.

A typical mechanical oscillator is unsatisfactory because it will usually be sending out 2 on signals at once, one from the pressure plate the water is on and the other from the pressure plate waiting to reset.

This diagram shows a 12 step 6 signal oscillator. At the locations marked 0, there are no pressure plates. A lever operates the mechanism. When the lever is in the ON position, the #%%0 pumps activate, and when the lever is in the OFF position, the 0%%# pumps activate. The oscillator can also be fully automated by using the pressure plates themselves to replace the lever function. The oscillator's power supply also needs to be cut if a halt signal is received from the control unit.  

This diagram shows a 12 step 6 signal oscillator. At the locations marked 0, there are no pressure plates. A lever operates the mechanism. When the lever is in the ON position, the #%%0 pumps activate, and when the lever is in the OFF position, the 0%%# pumps activate. The oscillator can also be fully automated by using the pressure plates themselves to replace the lever function. The oscillator's power supply also needs to be cut if a halt signal is received from the control unit.  

#Read accumulator, write AR2, write IR, write MAR<br>

#Read accumulator, write AR2, write IR, write MAR<br>

A dump operation can be performed by telling the memory register to write when its linked inputs are inactive, effectively writing 0s.  

A dump operation can be performed by telling the memory register to write when its linked inputs are inactive, effectively writing 0s.  

The control unit can be implemented simply as a 3-8 decoder with appropriately linked pressure plates. The execute signal controlled gear assembly is located at the root of the decoder.  

The control unit can be implemented simply as a 3-8 decoder with appropriately linked pressure plates. The execute signal controlled gear assembly is located at the root of the decoder.  

:O6. Read memory, read MAR, activate decoder, Send Shift right signal to ALU (SHR select), write accumulator<br>

:O6. Read memory, read MAR, activate decoder, Send Shift right signal to ALU (SHR select), write accumulator<br>

:O7. Cut power to oscillator.<br>

:O7. Cut power to oscillator.<br>