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Uploads by Jong
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This special page shows all uploaded files.
| Date | Name | Thumbnail | Size | Description | Versions |
|---|---|---|---|---|---|
| 08:10, 30 April 2010 | Memreg.png (file) |  |
5 KB | Schematic of an 8-bit register | 1 |
| 08:15, 30 April 2010 | 2nscheme.png (file) |  |
2 KB | Schematic of a 2 to 4 decoder | 1 |
| 08:17, 30 April 2010 | 5nscheme.png (file) |  |
14 KB | Schematic of a 5 to 32 decoder | 1 |
| 08:19, 30 April 2010 | Memarchi.png (file) |  |
18 KB | Schematic of the memory unit's architecture | 1 |
| 08:23, 30 April 2010 | Rippleaddersubtracter.png (file) |  |
21 KB | Schematic of an 8-bit ripple-carry adder-subtractor | 1 |
| 08:26, 30 April 2010 | Carrycircuit.png (file) |  |
13 KB | Schematic of a carry calculation circuit for a carry-look-ahead adder | 1 |
| 08:29, 30 April 2010 | 175px-Rotate right arithmetically.svg.png (file) |  |
5 KB | Bitshift right (adapted from Wikipedia http://en.wikipedia.org/wiki/File:Rotate_right_logically.svg) | 1 |
| 08:31, 30 April 2010 | Rotate left logically.svg.png (file) |  |
5 KB | Bitshift Left (adapted from Wikipedia http://en.wikipedia.org/wiki/File:Rotate_left_logically.svg) | 1 |
| 08:32, 30 April 2010 | Aluarchi.png (file) |  |
27 KB | Schematic of the ALU architecture | 1 |
| 08:34, 30 April 2010 | ALUmulti.png (file) |  |
26 KB | Schematic of a ALU multiplexer implementation | 1 |
| 08:36, 30 April 2010 | Datatransfers.png (file) |  |
13 KB | Schematic of the data transfers within the CPU | 1 |
| 09:07, 30 April 2010 | DCOverview.png (file) |  |
55 KB | Overview of the Dwarven Computer | 1 |
| 09:19, 30 April 2010 | Single stage adder.png (file) |  |
45 KB | Schematic of a single-stage carry-look ahead adder. The gears indicated by the lighter circles are disengaged by default while the gears indicated by th bold coloured circles are engaged by default. Gears labeled with multiple letters indicates that mul | 1 |
