- v50 information can now be added to pages in the main namespace. v0.47 information can still be found in the DF2014 namespace. See here for more details on the new versioning policy.
- Use this page to report any issues related to the migration.
User:Hussell/DataFlipFlop
Data Flip-Flop[edit]
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
┼
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
┼
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈ is a water source (preferably infinite)
┼ are doors controlled by the Data input.
┼ are doors controlled by the Clock input.
^ and ^ are 0-6 pressure plates controlling the doors of the same colors, respectively.
> are downward stairways acting as unpressurized drains.
^, ^, ^, and ^ are 7-7 pressure plates controlling the doors of the same colors.
3 is 3/7 water.
This Data Flip-Flop has two inputs (Clock and Data), and one output (^ and its inverse ^). Unlike the Data Latch, in which the output matches the Data signal as long as the Clock signal is on, the Data Flip-flop takes on the value of the Data signal at the exact time the Clock signal flips from off to on, and remains frozen the rest of the time. This device is made from a Data Latch in sequence with a Clocked Set/Reset Latch.
Initial state, Clock CLOSED, Data CLOSED, output CLOSED:
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
┼
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
┼
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
┼
|
3
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
4
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
What happens after Data is OPENED:
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
┼
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
7
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
4
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
^ signals CLOSE, ^ signals OPEN:
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
┼
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
7
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
┼
|
4
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
2
|
3
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
^ signals CLOSE:
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
┼
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
┼
|
4
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
2
|
3
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
Steady state, Data is OPEN, Clock is CLOSED, and Output is still CLOSED.
What happens now when Clock is OPENED:
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
┼
|
4
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
7
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
┼
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
^ signals CLOSE and ^ signals OPEN:
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
4
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
7
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
┼
|
3
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
^ signals CLOSE:
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
| |
█
|
█
|
█
|
>
|
█
| |
≈
|
7
|
^
|
█
|
█
| |
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
┼
|
┼
|
4
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
7
|
┼
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
≈
|
7
|
┼
|
3
|
^
|
█
|
█
|
█
|
█
|
█
|
█
|
█
|
Steady state, with Data OPEN, Clock OPEN, and Output OPEN.
There are a variety of other steady states this device can have, but the output only changes if the Data input is different from the current output at the time the clock switches from CLOSED to OPEN.