Latest revision as of 16:54, 8 June 2021

Dwarftel Core d1[edit]

The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.

Registers[edit]

A	Main register, input of arithmetic operators and where the results are written.
B	Secondary register, most operations that need two inputs will use this register.
C	Conditional register, involved in low-level if statements.
PC	Program counter which keeps track of the memory address for the next instruction.

Instructions[edit]

0x0	Halt.
0x1	Load memory address to A.
0x2	Copy A to B.
0x3	Copy A to C.
0x4	Copy A to PC if C is not 0.
0x5	Store A to memory address.
0x6	\---
0x7	\---
0x8	Add A + B. Write result to A.
0x9	Increment 1 to A.
0xA	Subtract A - B. Write result to A.
0xB	Decrement 1 from A.
0xC	Shift A left by given amount.
0xD	Shift A right by given amount.
0xE	Bitwise A and B. Write result to A.
0xF	Bitwise not A. Write result to A.

Memory Cell[edit]

Single bit cell[edit]

Design for single bit memory cell found here

Byte cell[edit]

Design for byte:

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The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.

Memory write[edit]

Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the ☼ northern gear and the ☼ sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.

Memory read[edit]

The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.

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In the design, each row of red gear assemblies ☼ are linked to the row of pressure plates in a byte. The purple gear assemblies ☼ are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a power to signal converter (pts converter).

Binary Decoder[edit]

I will be using Jong's design for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.

Adder[edit]

The adder used in the Dwarftel Core d1 is a kogge-stone adder, which is a type of carry-lookahead adder. It consists of 3 components chained in a certain way.

Components:

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In the and gate, power is fed to the rightmost gear assembly. Both gear assemblies are inverted. Each gear assembly is linked to one input, power goes into the pts converter only when both inputs are open.

In the xor gate, power is fed to the gear assembly. The gear assembly is inverted and linked to both inputs. When either input, but not both, are open, power goes to the pts converter.

In the last component, there are three non-commutative inputs. Power is fed to the green gear assembly ☼. Input z is linked to the red gear assembly ☼. Inputs x and y are linked to either blue gear assembly ☼, creating an and gate. Both blue gears and the reg gear are inverted.

The adder takes the following steps:

G0i = Ai and Bi. P0i = Ai xor Bi (both for 0 ≤ i < 8)
G1i = (P0i and G0(i-1)) or G0i. P1i = P0i and P0(i-1) (both for 1 ≤ i < 8)
G2i = (P1i and G1(i-2)) or G1i. P2i = P1i and P1(i-2) (both for 2 ≤ i < 8)
G3i = (P2i and G2(i-4)) or G2i. P3i = P2i and P2(i-4) (both for 4 ≤ i < 8)
Si = P(last)i xor G(last)(i-1)

Where i is the bit index on the byte (0 being the least significant bit and 7 being the most significant bit). A and B are the registers used as inputs. P(last)i is the latest iteration of Pi. For example, P(last)1 is P1,1, since steps 3 and 4 don't apply to i=1. Similarly, G(last)i is the latest iteration of Gi.

The only delays are caused by pressure plates which turn off 99 ticks after a minecart stops pressing it. Just to be safe (and because minecarts might require some travel time) I will assume 103 ticks of delay per step. Since there's 5 steps in the process, there's a total of 515 ticks

Edge Detectors (Rising and Falling)[edit]

Rising edge detector design:

╔	╢	┼	╢	┼	^	╗
╚	═	═	═	═	═	╝

The rising edge detector sends a pulse when an open signal is sent. Both rollers ╢ are always active and sending the cart from west to east. The red door ┼ is linked to the input. The input is also connected to a not gate, which feeds to a pts converter. The pts converter connects to the red door ┼. The pressure plate ^ is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.

The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.

@@ Line 1: / Line 1: @@
 =Dwarftel Core d1=
+The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.
+==Registers==
+{| class="wikitable"
+|-
+|A
+|Main register, input of arithmetic operators and where the results are written.
+|-
+|B
+|Secondary register, most operations that need two inputs will use this register.
+|-
+|C
+|Conditional register, involved in low-level if statements.
+|-
+|PC
+|Program counter which keeps track of the memory address for the next instruction.
+|}
+==Instructions==
+{|class="wikitable"
+|-
+|0x0
+|Halt.
+|-
+|0x1
+|Load memory address to A.
+|-
+|0x2
+|Copy A to B.
+|-
+|0x3
+|Copy A to C.
+|-
+|0x4
+|Copy A to PC if C is not 0.
+|-
+|0x5
+|Store A to memory address.
+|-
+|0x6
+|\---
+|-
+|0x7
+|\---
+|-
+|0x8
+|Add A + B. Write result to A.
+|-
+|0x9
+|Increment 1 to A.
+|-
+|0xA
+|Subtract A - B. Write result to A.
+|-
+|0xB
+|Decrement 1 from A.
+|-
+|0xC
+|Shift A left by given amount.
+|-
+|0xD
+|Shift A right by given amount.
+|-
+|0xE
+|Bitwise A and B. Write result to A.
+|-
+|0xF
+|Bitwise not A. Write result to A.
+|}
 ==Memory Cell==
-Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]
+===Single bit cell===
-Design for byte
+Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br>
+===Byte cell===
+Design for byte:
 <diagram fg=7:0>
 O[%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%203][%205][%205][%203][%187]
-[#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188][#7:1][%210][#][#2:1][%15][#][%200][%188]
+[#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188][#7:1][%210][#2:1][%15][#][%200][%188]
+[#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15][#7:1][%186][#]O[#7:1][%210][#2:1][%15]
+[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O[#7:1][%208][#2:0][%15][#7:1][%186][#]O
+[%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#][%201][%187][#7:1][%208][#2:0][%15][#]
+[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O
+</diagram>
+The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.
+===Memory write===
+Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.
+===Memory read===
+The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.
+<diagram fg=6:0>
+<frame type=level level=1>
+ [%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]
+ [#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]
+ [%186]
+ [%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]
+ [#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]
+ [%186]
+ [%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]
+ [#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#]
+ [%186]
+ [%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]
+ [#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]
+ .
+ .           Z=1
+ .[#]
+ [%186][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15]
+ [#7:0][%15][#5:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15][#6:0][%205][#7:0][%15]
+</frame>
+<frame type=level level=0>
+[#7:0]OO  OO  OO  OO
+[#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]
+[#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186] [#7:1][%200][%188][#][%186]
+  [#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]
+  ║ ║ ║ ║ ║ ║ ║
+  ║ ║ ║ ║ ║ ║ ║
+  [#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]
+  ║ ║ ║ ║ ║ ║ ║
+  ║ ║ ║ ║ ║ ║ ║
+  [#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]
+  ║ ║ ║ ║ ║ ║ ║
+  ║ ║ ║ ║ ║ ║ ║
+  [#7:0]☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼[#]
+  ║ ║ ║ ║ ║ ║ ║
+  [#7:0].
+  .          Z=0
+  .
+  ☼ ☼ ☼ ☼ ☼ ☼ ☼ ☼
+  OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186] [#7:0]OO[#6:0][%186]
+  [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15] [#5:1]^[#0:0][@7:0][%254][@][#2:1][%15]
+  [#7:1][%200][%188]  [%200][%188]  [%200][%188]  [%200][%188]
+</frame>
+</diagram>
+In the design, each row of red gear assemblies {{Raw Tile|☼|4:1}} are linked to the row of pressure plates in a byte. The purple gear assemblies {{Raw Tile|☼|5:0}} are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a [[Mechanical_logic#Power_to_signal_converter|power to signal converter]] (pts converter).
+==Binary Decoder==
+I will be using [[User:Jong/Dwarven_Computer#Decoder|Jong's design]] for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.
+==Adder==
+The adder used in the Dwarftel Core d1 is a kogge-stone adder, which is a type of carry-lookahead adder. It consists of 3 components chained in a certain way.
+Components:
+<diagram fg=7:0>
+O══════════════════O
+[#5:1]^[#0:0][@7:0]■[@][#1:1]☼☼[#]  And gate
+[#7:1]╚╝[#]
+O══════════════════O
+[#5:1]^[#0:0][@7:0]■[@][#4:1]☼[#]   Xor gate
+[#7:1]╚╝[#]
+O══════════════════O
+OO[#]☼[#4:1]☼[#2:1]☼[#] (x and y) or z
+[#5:1]^[#0:0][@7:0]■[@#]☼[#1:1]☼☼
+[#7:1]╚╝
+</diagram>
+In the and gate, power is fed to the rightmost gear assembly. Both gear assemblies are inverted. Each gear assembly is linked to one input, power goes into the pts converter only when both inputs are open.
+In the xor gate, power is fed to the gear assembly. The gear assembly is inverted and linked to both inputs. When either input, but not both, are open, power goes to the pts converter.
+In the last component, there are three non-commutative inputs. Power is fed to the green gear assembly {{Raw Tile|☼|#0F0}}. Input z is linked to the red gear assembly {{Raw Tile|☼|#F00}}. Inputs x and y are linked to either blue gear assembly {{Raw Tile|☼|#00F}}, creating an and gate. Both blue gears and the reg gear are inverted.
+The adder takes the following steps:
+# G0i = Ai and Bi. P0i = Ai xor Bi (both for 0 ≤ i < 8)
+# G1i = (P0i and G0(i-1)) or G0i. P1i = P0i and P0(i-1) (both for 1 ≤ i < 8)
+# G2i = (P1i and G1(i-2)) or G1i. P2i = P1i and P1(i-2) (both for 2 ≤ i < 8)
+# G3i = (P2i and G2(i-4)) or G2i. P3i = P2i and P2(i-4) (both for 4 ≤ i < 8)
+# Si = P(last)i xor G(last)(i-1)
+Where i is the bit index on the byte (0 being the least significant bit and 7 being the most significant bit). A and B are the registers used as inputs. P(last)i is the latest iteration of Pi. For example, P(last)1 is P1,1, since steps 3 and 4 don't apply to i=1. Similarly, G(last)i is the latest iteration of Gi.
+[[File:Kogge stone adder diagram.png|450px|The image shows how each step of the adder connects to the next step(s).]]
+The only delays are caused by pressure plates which turn off 99 ticks after a minecart stops pressing it. Just to be safe (and because minecarts might require some travel time) I will assume 103 ticks of delay per step. Since there's 5 steps in the process, there's a total of 515 ticks
+==Edge Detectors (Rising and Falling)==
+Rising edge detector design:
+<diagram fg=7:1>
+╔[#7:0]╢[@4:1]┼[@]╢[@2:1]┼[@][#5:1]^[#]╗
+╚═════╝
 </diagram>
+The rising edge detector sends a pulse when an open signal is sent. Both rollers {{Raw Tile|╢|7:0}} are always active and sending the cart from west to east. The red door {{Raw Tile|┼|#C0C0C0|#F00}} is linked to the input. The input is also connected to a not gate, which feeds to a pts converter. The pts converter connects to the red door {{Raw Tile|┼|#C0C0C0|#0F0}}. The pressure plate {{Raw Tile|^|5:1}} is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.
+The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.

Difference between revisions of "User:Green Sprite"