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Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. | Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the {{Raw Tile|☼|#0F0}} northern gear and the {{Raw Tile|☼|#080}} sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. | ||
===Memory read=== | ===Memory read=== | ||
| + | <diagram fg=7:0> | ||
| + | <frame type=level level=1> | ||
| + | [#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#] | ||
| + | [#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#] | ||
| + | [#6:0][%186][#] | ||
| + | [#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#] | ||
| + | [#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#] | ||
| + | [#6:0][%186][#] | ||
| + | [#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#] | ||
| + | [#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#] | ||
| + | [#6:0][%186][#] | ||
| + | [#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#] | ||
| + | [#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#] | ||
| + | . | ||
| + | . Z=1 | ||
| + | . | ||
| + | [#6:0][%186][#][#4:1][%15] [%15] [%15] [%15] [%15] [%15] [%15] [%15][#] | ||
| + | [#7:0][%15][#][#5:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#][#6:0][%205][#][#7:0][%15][#] | ||
| + | </frame> | ||
| + | <frame type=level level=0> | ||
| + | [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | . | ||
| + | . Z=0 | ||
| + | . | ||
| + | [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] [#7:0][%15][#] | ||
| + | [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] [#6:0][%186][#] | ||
| + | </frame> | ||
| + | </diagram> | ||
Revision as of 05:44, 5 June 2021
Dwarftel Core d1
Memory Cell
Single bit cell
Design for single bit memory cell found here
Byte cell
Design for byte:
| O | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╗ |
| ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ |
| ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ |
| ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O |
| ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ |
| ╚ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | O |
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.
Memory write
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the ☼ northern gear and the ☼ sourthern gear assembly of the respective bit of all bytes in memory. The northern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off.
Memory read
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ |
| ║ | |||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ |
| ║ | |||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ |
| ║ | |||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ |
| . | |||||||||||||||
| . | Z | = | 1 | ||||||||||||
| . | |||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ |
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | ||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | ||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | ||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | ||||||||
| . | |||||||||||||||
| . | Z | = | 0 | ||||||||||||
| . | |||||||||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ |