Dwarftel Core d1

The Dwarftel Core d1 is a dwarven computer that uses primarily toggle-based mechanical logic. It is a simple processor that can add, subtract, binary shift, perform bitwise 'and' and 'not'. The processor also has 16 bytes of memory which it can write and read to. The program is kept on the memory.

Registers

A	Main register, input of arithmetic operators and where the results are written.
B	Secondary register, most operations that need two inputs will use this register.
C	Conditional register, involved in low-level if statements.
PC	Program counter which keeps track of the memory address for the next instruction.

Instructions

0x0	Halt.
0x1	Load memory address to A.
0x2	Copy A to B.
0x3	Copy A to C.
0x4	Copy A to PC if C is not 0.
0x5	Store A to memory address.
0x6	\---
0x7	\---
0x8	Add A + B. Write result to A.
0x9	Increment 1 to A.
0xA	Subtract A - B. Write result to A.
0xB	Decrement 1 from A.
0xC	Shift A left by given amount.
0xD	Shift A right by given amount.
0xE	Bitwise A and B. Write result to A.
0xF	Bitwise not A. Write result to A.

Memory Cell

Single bit cell

Design for single bit memory cell found here

Byte cell

Design for byte:

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The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.

Memory write

Multiple byte cells are created close together to create the actual memory. A register for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the register connects to the ☼ northern gear and the ☼ sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.

Memory read

The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.

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In the design, each row of red gear assemblies ☼ are linked to the row of pressure plates in a byte. The purple gear assemblies ☼ are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a power to signal converter.

Binary Decoder

I will be using Jong's design for a binary decoder. Binary decoders allow for memory addressing and selecting operations from an opcode.

Adder

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Kogge-Stone Adder

Edge Detectors (Rising and Falling)

Rising edge detector design:

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The rising edge detector sends a pulse when an open signal is sent. Both rollers ╢ are always active and sending the cart from west to east. The red door ┼ is linked to the input. The input is also connected to a not gate, which feeds to a power to signal converter. The power to signal converter connects to the red door ┼. The pressure plate ^ is the output. A minecart is placed on the roller between both doors. When the input sends a open signal the green door opens, letting the minecart past the pressure plate. The pressure plate sends a pulse starting instantly for 99 ticks. At the same time, the red door closes, stopping the minecart from going through. When the input sends a closed signal again, the red door opens, but the green door closes, so the minecart is set back to the original position.

The falling edge detector is the same as the rising edge detector, but the green and red doors are flipped.

User:Green Sprite

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