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User:Green Sprite
Dwarftel Core d1
Memory Cell
Single bit cell
Design for single bit memory cell found here
Byte cell
Design for byte:
| O | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╗ |
| ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ |
| ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ |
| ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O |
| ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ |
| ╚ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | O |
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.
Memory write
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in each bit of the registry connects to the ☼ northern gear and the ☼ sourthern gear assembly of the respective bit of all bytes in memory. The southern gear assembly is inverted. On a layer above, power is provided to all of the gears assemblies of each byte. A binary decoder selects a byte to activate in the layer above. Writing works by letting power flow first only to the byte being written to, and then the individual bits being turned on or off. To minimize the number of linkages in the reading of memory, the pressure plate being activated corresponds to a 0, and the pressure plate being lifted (unactivated) corresponds to a 1.
Memory read
The following diagram has multiple z-levels, click the diagram and press < or > to go up and down.
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | |
| ║ | ||||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | |
| ║ | ||||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | |
| ║ | ||||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | |
| . | ||||||||||||||||
| . | Z | = | 1 | |||||||||||||
| . | ||||||||||||||||
| ║ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ||||||||
| ☼ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ | ═ | ☼ |
| O | O | O | O | O | O | O | O | |||||||||
| ^ | ■ | ☼ | ^ | ■ | ☼ | ^ | ■ | ☼ | ^ | ■ | ☼ | |||||
| ╚ | ╝ | ║ | ╚ | ╝ | ║ | ╚ | ╝ | ║ | ╚ | ╝ | ║ | |||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | |||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | |||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | |||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | |||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | |||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | |||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||||
| ║ | ║ | ║ | ║ | ║ | ║ | ║ | ║ | |||||||||
| . | ||||||||||||||||
| . | Z | = | 0 | |||||||||||||
| . | ||||||||||||||||
| ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | ☼ | |||||||||
| O | O | ║ | O | O | ║ | O | O | ║ | O | O | ║ | |||||
| ^ | ■ | ☼ | ^ | ■ | ☼ | ^ | ■ | ☼ | ^ | ■ | ☼ | |||||
| ╚ | ╝ | ╚ | ╝ | ╚ | ╝ | ╚ | ╝ |
In the design, each row of red gear assemblies ☼ are linked to the row of pressure plates in a byte. The purple gear assemblies ☼ are normally inverted and decide which byte to read. A binary decoder selects which purple gear assembly to engage. Reading works by first letting power flow through a single purple gear assembly corresponding to one byte and then through the red gear assemblies that are engaged. The lower z level (0) carries the power to a power to signal converter.